Struct rust_hdl_widgets::registered_edge_tristate::RegisteredEdgeTristate

pub struct RegisteredEdgeTristate<const W: usize> {
    pub bus: Signal<InOut, Bits<W>>,
    pub write_enable: Signal<In, Bit>,
    pub write_data: Signal<In, Bits<W>>,
    pub read_data: Signal<Out, Bits<W>>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

bus: Signal<InOut, Bits<W>>

write_enable: Signal<In, Bit>

write_data: Signal<In, Bits<W>>

read_data: Signal<Out, Bits<W>>

clock: Signal<In, Clock>

Trait Implementations

impl<const W: usize> Block for RegisteredEdgeTristate<W>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const W: usize> Default for RegisteredEdgeTristate<W>

fn default() -> RegisteredEdgeTristate<W>

Returns the “default value” for a type.

impl<const W: usize> Logic for RegisteredEdgeTristate<W>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>