Struct rust_hdl_sim::muxed_ad7193_sim::MuxedAD7193Simulators

pub struct MuxedAD7193Simulators {
    pub wires: SPIWiresSlave,
    pub addr: Signal<In, Bits<3>>,
    pub mux: MuxSlaves<8, 3>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

wires: SPIWiresSlave

addr: Signal<In, Bits<3>>

mux: MuxSlaves<8, 3>

clock: Signal<In, Clock>

Implementations

impl MuxedAD7193Simulators

pub fn new(config: AD7193Config) -> Self

Trait Implementations

impl Block for MuxedAD7193Simulators

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Logic for MuxedAD7193Simulators

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>