Struct rust_hdl_sim::sdr_sdram::chip::SDRAMSimulator

pub struct SDRAMSimulator<const R: usize, const C: usize, const A: usize, const D: usize> {
    pub sdram: SDRAMDevice<D>,
    pub test_error: Signal<Out, Bit>,
    pub test_ready: Signal<Out, Bit>,
    /* private fields */
}

Fields

sdram: SDRAMDevice<D>

test_error: Signal<Out, Bit>

test_ready: Signal<Out, Bit>

Implementations

impl<const R: usize, const C: usize, const A: usize, const D: usize> SDRAMSimulator<R, C, A, D>

pub fn new(timings: MemoryTimings) -> Self

Trait Implementations

impl<const R: usize, const C: usize, const A: usize, const D: usize> Block for SDRAMSimulator<R, C, A, D>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const R: usize, const C: usize, const A: usize, const D: usize> Logic for SDRAMSimulator<R, C, A, D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>