1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143

use rust_hdl_core::prelude::*;

#[derive(Clone, Debug, LogicBlock)]
pub struct TriggerOut {
    pub ok1: Signal<In, Bits<31>>,
    pub ok2: Signal<Out, Bits<17>>,
    pub clk: Signal<In, Clock>,
    pub trigger: Signal<In, Bits<16>>,
    _n: u8,
}

impl TriggerOut {
    pub fn new(n: u8) -> Self {
        assert!(n >= 60 && n < 0x80);
        Self {
            ok1: Default::default(),
            ok2: Default::default(),
            clk: Default::default(),
            trigger: Default::default(),
            _n: n,
        }
    }
}

impl Logic for TriggerOut {
    fn update(&mut self) {}
    fn connect(&mut self) {
        self.ok2.connect();
    }
    fn hdl(&self) -> Verilog {
        let name = format!("TriggerOut_{:x}", self._n);
        Verilog::Blackbox(BlackBox {
            code: format!(
                r#"
module {}
    (
    input wire [30:0] ok1,
    output wire [16:0] ok2,
    input wire        clk,
    input wire [15:0] trigger
    );

    okTriggerOut mod_trigger(.ok1(ok1),
                             .ok2(ok2),
                             .ep_addr({:x}),
                             .ep_clk(clk),
                             .ep_trigger(trigger));
endmodule

(* blackbox *)
module okTriggerOut(
    input wire [30:0]  ok1,
    output wire [16:0] ok2,
    input wire [7:0]   ep_addr,
    input wire         ep_clk,
    input wire [15:0]  ep_trigger
);
endmodule  "#,
                name,
                VerilogLiteral::from(self._n)
            ),
            name,
        })
    }
}

#[test]
fn test_trigger_out() {
    let mut uut = rust_hdl_yosys_synth::TopWrap::new(TriggerOut::new(0x60));
    uut.uut.ok1.connect();
    uut.uut.clk.connect();
    uut.uut.trigger.connect();
    uut.connect_all();
    rust_hdl_yosys_synth::yosys_validate("trigout", &generate_verilog(&uut)).unwrap();
}

#[derive(Clone, Debug, LogicBlock)]
pub struct TriggerIn {
    pub ok1: Signal<In, Bits<31>>,
    pub clk: Signal<In, Clock>,
    pub trigger: Signal<Out, Bits<16>>,
    _n: u8,
}

impl TriggerIn {
    pub fn new(n: u8) -> Self {
        assert!(n >= 0x40 && n < 0x60);
        Self {
            ok1: Default::default(),
            clk: Default::default(),
            trigger: Default::default(),
            _n: n,
        }
    }
}

impl Logic for TriggerIn {
    fn update(&mut self) {}
    fn connect(&mut self) {
        self.trigger.connect();
    }
    fn hdl(&self) -> Verilog {
        let name = format!("TriggerIn_{:x}", self._n);
        Verilog::Blackbox(BlackBox {
            code: format!(
                r#"
module {}
    (
    input wire [30:0] ok1,
    input wire        clk,
    output wire [15:0] trigger
    );

    okTriggerIn mod_trigger(.ok1(ok1),
                            .ep_addr({:x}),
                            .ep_clk(clk),
                            .ep_trigger(trigger));
endmodule

(* blackbox *)
module okTriggerIn(
    input wire [30:0]  ok1,
    input wire [7:0]   ep_addr,
    input wire         ep_clk,
    output wire [15:0] ep_trigger
);
endmodule  "#,
                name,
                VerilogLiteral::from(self._n)
            ),
            name,
        })
    }
}

#[test]
fn test_trigger_in() {
    let mut uut = rust_hdl_yosys_synth::TopWrap::new(TriggerIn::new(0x40));
    uut.uut.ok1.connect();
    uut.uut.clk.connect();
    uut.connect_all();
    rust_hdl_yosys_synth::yosys_validate("trigin", &generate_verilog(&uut)).unwrap();
}