Struct rust_hdl_fpga_support::lattice::ice40::ice_pll::ICE40PLLBlock

pub struct ICE40PLLBlock<const FIN_FREQ: u64, const FOUT_FREQ: u64> {
    pub clock_in: Signal<In, Clock>,
    pub clock_out: Signal<Out, Clock>,
    pub locked: Signal<Out, Bit>,
    /* private fields */
}

Fields

clock_in: Signal<In, Clock>

clock_out: Signal<Out, Clock>

locked: Signal<Out, Bit>

Trait Implementations

impl<const FIN_FREQ: u64, const FOUT_FREQ: u64> Block for ICE40PLLBlock<FIN_FREQ, FOUT_FREQ>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const FIN_FREQ: u64, const FOUT_FREQ: u64> Default for ICE40PLLBlock<FIN_FREQ, FOUT_FREQ>

fn default() -> Self

Returns the “default value” for a type.

impl<const FIN_FREQ: u64, const FOUT_FREQ: u64> Logic for ICE40PLLBlock<FIN_FREQ, FOUT_FREQ>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>