Struct rust_hdl_fpga_support::lattice::ecp5::oddr::OutputDDR

pub struct OutputDDR {
    pub d: Signal<In, Bits<2>>,
    pub clock: Signal<In, Clock>,
    pub q: Signal<Out, Bit>,
    pub reset: Signal<In, Bit>,
    /* private fields */
}

Fields

d: Signal<In, Bits<2>>

clock: Signal<In, Clock>

q: Signal<Out, Bit>

reset: Signal<In, Bit>

Trait Implementations

impl Block for OutputDDR

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Clone for OutputDDR

fn clone(&self) -> OutputDDR

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for OutputDDR

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for OutputDDR

fn default() -> OutputDDR

Returns the “default value” for a type.

impl Logic for OutputDDR

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>