Struct rust_hdl_fpga_support::lattice::ecp5::io_delay::IODelay

pub struct IODelay<T: Synth> {
    pub a: Signal<In, T>,
    pub z: Signal<Out, T>,
    /* private fields */
}

Fields

a: Signal<In, T>

z: Signal<Out, T>

Implementations

impl<T: Synth> IODelay<T>

pub fn new(delay: u8) -> Self

Trait Implementations

impl<T: Synth> Block for IODelay<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Clone + Synth> Clone for IODelay<T>

fn clone(&self) -> IODelay<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Synth> Debug for IODelay<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Synth> Logic for IODelay<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>