Struct rust_hdl_fpga_support::lattice::ecp5::edge_tristate_buffer::EdgeTristateBuffer

pub struct EdgeTristateBuffer<T: Synth> {
    pub to_pin: Signal<In, T>,
    pub from_pin: Signal<Out, T>,
    pub output_enable: Signal<In, Bit>,
    pub clock: Signal<In, Clock>,
    pub reset: Signal<In, Bit>,
    pub pin: Signal<InOut, T>,
    /* private fields */
}

Fields

to_pin: Signal<In, T>

from_pin: Signal<Out, T>

output_enable: Signal<In, Bit>

clock: Signal<In, Clock>

reset: Signal<In, Bit>

pin: Signal<InOut, T>

Trait Implementations

impl<T: Synth> Block for EdgeTristateBuffer<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Default + Synth> Default for EdgeTristateBuffer<T>

fn default() -> EdgeTristateBuffer<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for EdgeTristateBuffer<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>