List of all items

Structs

• ast::BlackBox
• ast::Wrapper
• check_error::PathedName
• clock::Clock
• constant::Constant
• constraint::FalsePathRegexp
• constraint::InputTimingConstraint
• constraint::OutputTimingConstraint
• constraint::PeriodicTiming
• constraint::PinConstraint
• constraint::VivadoInputTimingConstraint
• constraint::VivadoOutputTimingConstraint
• direction::In
• direction::InOut
• direction::Local
• direction::Out
• module_defines::ModuleDefines
• named_path::NamedPath
• signal::Signal
• signed::Signed
• simulate::Sim
• simulate::Simulation
• timing::TimingInfo
• top_wrap::TopWrap
• type_descriptor::TypeDescriptor
• type_descriptor::TypeField
• vcd_probe::VCDProbe

Enums

• ast::Verilog
• bits::Bits
• check_error::CheckError
• constraint::Constraint
• constraint::SignalType
• constraint::SlewType
• constraint::Timing
• constraint::TimingRelative
• constraint::TimingRelativeEdge
• simulate::SimError
• synth::VCDValue
• type_descriptor::TypeKind
• yosys::SynthError

Traits

• bits::ToBits
• block::Block
• logic::Logic
• logic::LogicJoin
• logic::LogicLink
• probe::Probe
• signed::ToSignedBits
• synth::Synth
• verilog_visitor::VerilogVisitor

Macros

• clock
• prelude::clock
• prelude::sim_assert
• prelude::sim_assert_eq
• prelude::simple_sim
• prelude::target_path
• prelude::vcd_path
• prelude::wait_clock_cycle
• prelude::wait_clock_cycles
• prelude::wait_clock_false
• prelude::wait_clock_true
• sim_assert
• sim_assert_eq
• simple_sim
• target_path
• vcd_path
• wait_clock_cycle
• wait_clock_cycles
• wait_clock_false
• wait_clock_true

Attribute Macros

• prelude::hdl_gen

Derive Macros

• prelude::LogicBlock
• prelude::LogicInterface
• prelude::LogicState
• prelude::LogicStruct

Functions

• bits::bit_cast
• bits::bits
• bits::clog2
• check_connected::check_connected
• check_error::check_all
• check_logic_loops::check_logic_loops
• check_timing::check_timing
• check_write_inputs::check_inputs_not_written
• clock::freq_hz_to_period_femto
• logic::logic_connect_fn
• logic::logic_connect_join_fn
• logic::logic_connect_link_fn
• module_defines::generate_verilog
• module_defines::generate_verilog_unchecked
• signal::get_signal_id
• signed::signed
• signed::signed_bit_cast
• signed::signed_cast
• signed::unsigned_bit_cast
• signed::unsigned_cast
• simulate::simulate
• vcd_probe::write_vcd_change
• vcd_probe::write_vcd_dump
• vcd_probe::write_vcd_header
• verilog_gen::filter_blackbox_directives
• verilog_gen::verilog_combinatorial
• verilog_gen::verilog_link_extraction
• verilog_visitor::walk_assignment
• verilog_visitor::walk_binop
• verilog_visitor::walk_block
• verilog_visitor::walk_block_or_conditional
• verilog_visitor::walk_case
• verilog_visitor::walk_cast
• verilog_visitor::walk_conditional
• verilog_visitor::walk_expression
• verilog_visitor::walk_index
• verilog_visitor::walk_index_assignment
• verilog_visitor::walk_index_replacement
• verilog_visitor::walk_lhs_expression
• verilog_visitor::walk_loop
• verilog_visitor::walk_match
• verilog_visitor::walk_paren
• verilog_visitor::walk_signed
• verilog_visitor::walk_slice
• verilog_visitor::walk_slice_assignment
• verilog_visitor::walk_slice_replace
• verilog_visitor::walk_statement
• verilog_visitor::walk_unop
• verilog_visitor::walk_unsigned
• yosys::yosys_validate

Type Definitions

• bits::Bit
• bits::LiteralType
• check_error::OpenMap
• check_error::PathedNameList
• signed::SignedLiteralType
• simulate::CustomLogicFn
• simulate::Result

Constants

• bits::LITERAL_BITS
• clock::NANOS_PER_FEMTO
• signed::SIGNED_LITERAL_BITS
• simulate::SIMULATION_TIME_ONE_SECOND
• simulate::sim_time::ONE_MICROSECOND
• simulate::sim_time::ONE_MILLISECOND
• simulate::sim_time::ONE_NANOSECOND
• simulate::sim_time::ONE_PICOSECOND
• simulate::sim_time::ONE_SEC