Module rust_hdl_core::prelude
source · Re-exports
pub use crate::ast;pub use crate::ast::BlackBox;pub use crate::ast::Verilog;pub use crate::ast::VerilogLiteral;pub use crate::ast::Wrapper;pub use crate::atom::Atom;pub use crate::atom::AtomKind;pub use crate::bits::bit_cast;pub use crate::bits::bits;pub use crate::bits::clog2;pub use crate::bits::LiteralType;pub use crate::bits::ToBits;pub use crate::bits::Bit;pub use crate::bits::Bits;pub use crate::block;pub use crate::block::Block;pub use crate::check_connected::check_connected;pub use crate::check_error::check_all;pub use crate::check_timing::check_timing;pub use crate::clock;pub use crate::clock;pub use crate::clock::freq_hz_to_period_femto;pub use crate::clock::Clock;pub use crate::clock::NANOS_PER_FEMTO;pub use crate::constant::Constant;pub use crate::direction::Direction;pub use crate::direction::In;pub use crate::direction::InOut;pub use crate::direction::Local;pub use crate::direction::Out;pub use crate::logic;pub use crate::logic::Logic;pub use crate::logic::LogicJoin;pub use crate::logic::LogicLink;pub use crate::module_defines::ModuleDefines;pub use crate::module_defines::generate_verilog;pub use crate::module_defines::generate_verilog_unchecked;pub use crate::named_path::NamedPath;pub use crate::probe;pub use crate::probe::Probe;pub use crate::signal::Signal;pub use crate::signed::ToSignedBits;pub use crate::signed::signed;pub use crate::signed::signed_bit_cast;pub use crate::signed::signed_cast;pub use crate::signed::unsigned_bit_cast;pub use crate::signed::unsigned_cast;pub use crate::signed::Signed;pub use crate::simulate::sim_time;pub use crate::simulate::simulate;pub use crate::simulate::SIMULATION_TIME_ONE_SECOND;pub use crate::simulate::Sim;pub use crate::simulate::SimError;pub use crate::simulate::Simulation;pub use crate::synth;pub use crate::synth::Synth;pub use crate::synth::VCDValue;pub use crate::timing::TimingInfo;pub use crate::top_wrap::TopWrap;pub use crate::type_descriptor;pub use crate::type_descriptor::TypeDescriptor;pub use crate::type_descriptor::TypeField;pub use crate::type_descriptor::TypeKind;pub use crate::vcd_probe::write_vcd_change;pub use crate::vcd_probe::write_vcd_dump;pub use crate::vcd_probe::write_vcd_header;pub use crate::verilog_gen::filter_blackbox_directives;pub use crate::verilog_visitor::VerilogVisitor;pub use crate::constraint::Timing::*;pub use crate::constraint::*;pub use crate::yosys::*;
Macros
- The [clock!] macro is used to connect a set of devices to a common clock. The macro takes a variable number of arguments: