Module rust_hdl_core::clock

source ·

Structs

  • Fundamentally a Clock signal in RustHDL is simply a transparent wrapper around a boolean valued signal. So it could be thought of as a simple 1-bit wide signal. However, semantically, clocks are rarely treated like other signals, and typically connect only to dedicated clock ports on synchronous logic (like [DFF] or [RAM]).

Constants

Functions