Enum rust_hdl_core::ast::Verilog

pub enum Verilog {
    Empty,
    Custom(String),
    Blackbox(BlackBox),
    Wrapper(Wrapper),
    // some variants omitted
}

The Verilog type is used to represent the Verilog translation of a RustHDL kernel. You will only need it if implementing blackbox cores or wrapping external Verilog code.

Variants

Empty

Use [Empty] when you do not want a module represented in Verilog at all

Custom(String)

Custom Verilog for a RustHDL module

Blackbox(BlackBox)

Blackbox for referencing IP cores.

Wrapper(Wrapper)

Wrap an external IP core or Verilog code into a RustHDL module.

Trait Implementations

impl Clone for Verilog

fn clone(&self) -> Verilog

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Verilog

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Verilog

fn default() -> Self

Returns the “default value” for a type.