Enum rust_hdl_core::ast::VerilogStatement [−][src]
pub enum VerilogStatement {
Assignment(VerilogExpression, VerilogExpression),
SliceAssignment {
base: String,
width: usize,
offset: VerilogExpression,
replacement: VerilogExpression,
},
If(VerilogConditional),
Match(VerilogMatch),
Loop(VerilogLoop),
Comment(String),
Link(Vec<VerilogLink>),
}
Variants
Assignment(VerilogExpression, VerilogExpression)
Tuple Fields of Assignment
Fields of SliceAssignment
Tuple Fields of If
Match(VerilogMatch)
Tuple Fields of Match
0: VerilogMatch
Loop(VerilogLoop)
Tuple Fields of Loop
0: VerilogLoop
Comment(String)
Tuple Fields of Comment
0: String
Link(Vec<VerilogLink>)
Tuple Fields of Link
0: Vec<VerilogLink>
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for VerilogStatement
impl Send for VerilogStatement
impl Sync for VerilogStatement
impl Unpin for VerilogStatement
impl UnwindSafe for VerilogStatement
Blanket Implementations
Mutably borrows from an owned value. Read more