Enum Arch 

pub enum Arch {
    X86_64,
    X86,
    Aarch64,
    Arm,
    Arm64Ec,
    Riscv64,
    Riscv32,
    LoongArch64,
    PowerPc64,
    S390x,
    Wasm32,
}

An instruction set family.

Deliberately not #[non_exhaustive]. Adding a variant here has to break every match that needs to change, in this workspace and in anyone else’s code. That is the property spec/cross-compile/02-the-goal.md claim 3 is making when it says adding a target is a data change: the compiler tells you every place the data is read.

Variants

X86_64

x86-64. The reference target, and the one everything is measured against first.

X86

32-bit x86, from i686 upwards. Not a narrower x86-64: eight registers, a PIC base register, and x87 as the floating point unit of the base ABI.

Aarch64

64-bit ARM.

Arm

32-bit ARM, including Thumb.

Arm64Ec

ARM64EC. A 64-bit ARM instruction set with the x86-64 calling convention, its own symbol namespace and thunks between the two. spec/cross-compile/06-abis.md section 6.8 declines to implement it and spec/cross-compile/04-target-matrix.md keeps it at tier 4, so this variant exists so that the tuple parses and --print-config answers, and nothing emits code for it.

Riscv64

64-bit RISC-V.

Riscv32

32-bit RISC-V.

LoongArch64

64-bit LoongArch.

PowerPc64

64-bit PowerPC. Only ELFv2 is in scope, which is what makes the little-endian spelling the common one.

S390x

IBM z/Architecture. The big-endian row, and the reason byte order is a field.

Wasm32

WebAssembly with 32-bit addresses. A stack machine with structured control flow, which spec/cross-compile/05-architectures.md section 5.9 explains is a second back end rather than a tenth architecture.

Implementations

impl Arch

pub const fn as_str(self) -> &'static str

The canonical name, which is the leading component of a tuple for every architecture whose baseline is not spelled in that component. ARM is the exception and crate::TargetTuple handles it.

pub const fn register_width(self) -> u32

The width of a general purpose register, in bits.

This is a property of the instruction set and it is not the pointer width. A 64-bit machine running an ILP32 data model has 64-bit registers and 32-bit pointers, which is what x86_64-linux-gnux32 is for.

pub const fn default_endian(self) -> Endian

The byte order this architecture uses unless the tuple says otherwise.

Every architecture here except s390x is little-endian by default, and five of them have a big-endian mode that a real target uses. That is why endianness is a tuple field and not a constant on this enum: the version of this function that returned true for everything was wrong for aarch64, arm, riscv, powerpc and mips at the same time.

pub const fn has_both_endians(self) -> bool

Whether this architecture has a big-endian mode any target in the table uses.

x86 does not, so x86_64eb is a spelling error rather than a target, and saying so is better than emitting bytes for a machine that does not exist.

pub const fn takes_subarch(self) -> bool

Whether a sub-architecture may be spelled for this family.

pub const fn selects_float_abi(self) -> bool

Whether this family has more than one float calling convention to choose between.

False for x86-64, AArch64, s390x and PowerPC, which have exactly one, so naming a float ABI for them is a spelling error rather than a configuration. True for ARM, RISC-V and LoongArch, where it is a real choice that changes which registers arguments arrive in.

Trait Implementations

impl Clone for Arch

fn clone(&self) -> Arch

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Arch

impl Debug for Arch

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for Arch

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for Arch

impl Hash for Arch

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for Arch

fn cmp(&self, other: &Arch) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

fn clamp_to<R>(self, range: R) -> Self

where Self: Sized, R: ClampBounds<Self>,

🔬This is a nightly-only experimental API. (clamp_to)

Restrict a value to a certain range.

impl PartialEq for Arch

fn eq(&self, other: &Arch) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl PartialOrd for Arch

fn partial_cmp(&self, other: &Arch) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl StructuralPartialEq for Arch