Struct rp2040::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTRL>>

pub fn power_down(&mut self) -> POWER_DOWN_W<'_>

Bit 3 - When 1, the cache memories are powered down. They retain state,\n but can not be accessed. This reduces static power dissipation.\n Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n be enabled when powered down.\n Cache-as-SRAM accesses will produce a bus error response when\n the cache is powered down.

pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W<'_>

Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating)\n will produce a bus fault. When 0, these writes are silently ignored.\n In either case, writes to the 0x0 alias will deallocate on tag match,\n as usual.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses\n will go straight to the flash, without querying the cache. When enabled,\n cacheable XIP accesses will query the cache, and the flash will\n not be accessed if the tag matches and the valid bit is set.\n\n If the cache is enabled, cache-as-SRAM accesses have no effect on the\n cache data RAM, and will produce a bus error response.

impl W<u32, Reg<u32, _FLUSH>>

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 0 - Write 1 to flush the cache. This clears the tag memory, but\n the data memory retains its contents. (This means cache-as-SRAM\n contents is not affected by flush or reset.)\n Reading will hold the bus (stall the processor) until the flush\n completes. Alternatively STAT can be polled until completion.

impl W<u32, Reg<u32, _STREAM_ADDR>>

pub fn stream_addr(&mut self) -> STREAM_ADDR_W<'_>

Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO.\n Increments automatically after each flash access.\n Write the initial access address here before starting a streaming read.

impl W<u32, Reg<u32, _STREAM_CTR>>

pub fn stream_ctr(&mut self) -> STREAM_CTR_W<'_>

Bits 0:21 - Write a nonzero value to start a streaming read. This will then\n progress in the background, using flash idle cycles to transfer\n a linear data block from flash to the streaming FIFO.\n Decrements automatically (1 at a time) as the stream\n progresses, and halts on reaching 0.\n Write 0 to halt an in-progress stream, and discard any in-flight\n read, so that a new stream can immediately be started (after\n draining the FIFO and reinitialising STREAM_ADDR)

impl W<u32, Reg<u32, _CTRLR0>>

pub fn sste(&mut self) -> SSTE_W<'_>

Bit 24 - Slave select toggle enable

pub fn spi_frf(&mut self) -> SPI_FRF_W<'_>

Bits 21:22 - SPI frame format

pub fn dfs_32(&mut self) -> DFS_32_W<'_>

Bits 16:20 - Data frame size in 32b transfer mode\n Value of n -> n+1 clocks per frame.

pub fn cfs(&mut self) -> CFS_W<'_>

Bits 12:15 - Control frame size\n Value of n -> n+1 clocks per frame.

pub fn srl(&mut self) -> SRL_W<'_>

Bit 11 - Shift register loop (test mode)

pub fn slv_oe(&mut self) -> SLV_OE_W<'_>

Bit 10 - Slave output enable

pub fn tmod(&mut self) -> TMOD_W<'_>

Bits 8:9 - Transfer mode

pub fn scpol(&mut self) -> SCPOL_W<'_>

Bit 7 - Serial clock polarity

pub fn scph(&mut self) -> SCPH_W<'_>

Bit 6 - Serial clock phase

pub fn frf(&mut self) -> FRF_W<'_>

Bits 4:5 - Frame format

pub fn dfs(&mut self) -> DFS_W<'_>

Bits 0:3 - Data frame size

impl W<u32, Reg<u32, _CTRLR1>>

pub fn ndf(&mut self) -> NDF_W<'_>

Bits 0:15 - Number of data frames

impl W<u32, Reg<u32, _SSIENR>>

pub fn ssi_en(&mut self) -> SSI_EN_W<'_>

Bit 0 - SSI enable

impl W<u32, Reg<u32, _MWCR>>

pub fn mhs(&mut self) -> MHS_W<'_>

Bit 2 - Microwire handshaking

pub fn mdd(&mut self) -> MDD_W<'_>

Bit 1 - Microwire control

pub fn mwmod(&mut self) -> MWMOD_W<'_>

Bit 0 - Microwire transfer mode

impl W<u32, Reg<u32, _SER>>

pub fn ser(&mut self) -> SER_W<'_>

Bit 0 - For each bit:\n 0 -> slave not selected\n 1 -> slave selected

impl W<u32, Reg<u32, _BAUDR>>

pub fn sckdv(&mut self) -> SCKDV_W<'_>

Bits 0:15 - SSI clock divider

impl W<u32, Reg<u32, _TXFTLR>>

pub fn tft(&mut self) -> TFT_W<'_>

Bits 0:7 - Transmit FIFO threshold

impl W<u32, Reg<u32, _RXFTLR>>

pub fn rft(&mut self) -> RFT_W<'_>

Bits 0:7 - Receive FIFO threshold

impl W<u32, Reg<u32, _IMR>>

pub fn mstim(&mut self) -> MSTIM_W<'_>

Bit 5 - Multi-master contention interrupt mask

pub fn rxfim(&mut self) -> RXFIM_W<'_>

Bit 4 - Receive FIFO full interrupt mask

pub fn rxoim(&mut self) -> RXOIM_W<'_>

Bit 3 - Receive FIFO overflow interrupt mask

pub fn rxuim(&mut self) -> RXUIM_W<'_>

Bit 2 - Receive FIFO underflow interrupt mask

pub fn txoim(&mut self) -> TXOIM_W<'_>

Bit 1 - Transmit FIFO overflow interrupt mask

pub fn txeim(&mut self) -> TXEIM_W<'_>

Bit 0 - Transmit FIFO empty interrupt mask

impl W<u32, Reg<u32, _DMACR>>

pub fn tdmae(&mut self) -> TDMAE_W<'_>

Bit 1 - Transmit DMA enable

pub fn rdmae(&mut self) -> RDMAE_W<'_>

Bit 0 - Receive DMA enable

impl W<u32, Reg<u32, _DMATDLR>>

pub fn dmatdl(&mut self) -> DMATDL_W<'_>

Bits 0:7 - Transmit data watermark level

impl W<u32, Reg<u32, _DMARDLR>>

pub fn dmardl(&mut self) -> DMARDL_W<'_>

Bits 0:7 - Receive data watermark level (DMARDLR+1)

impl W<u32, Reg<u32, _DR0>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - First data register of 36

impl W<u32, Reg<u32, _RX_SAMPLE_DLY>>

pub fn rsd(&mut self) -> RSD_W<'_>

Bits 0:7 - RXD sample delay (in SCLK cycles)

impl W<u32, Reg<u32, _SPI_CTRLR0>>

pub fn xip_cmd(&mut self) -> XIP_CMD_W<'_>

Bits 24:31 - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)

pub fn spi_rxds_en(&mut self) -> SPI_RXDS_EN_W<'_>

Bit 18 - Read data strobe enable

pub fn inst_ddr_en(&mut self) -> INST_DDR_EN_W<'_>

Bit 17 - Instruction DDR transfer enable

pub fn spi_ddr_en(&mut self) -> SPI_DDR_EN_W<'_>

Bit 16 - SPI DDR transfer enable

pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W<'_>

Bits 11:15 - Wait cycles between control frame transmit and data reception (in SCLK cycles)

pub fn inst_l(&mut self) -> INST_L_W<'_>

Bits 8:9 - Instruction length (0/4/8/16b)

pub fn addr_l(&mut self) -> ADDR_L_W<'_>

Bits 2:5 - Address length (0b-60b in 4b increments)

pub fn trans_type(&mut self) -> TRANS_TYPE_W<'_>

Bits 0:1 - Address and instruction transfer format

impl W<u32, Reg<u32, _TXD_DRIVE_EDGE>>

pub fn tde(&mut self) -> TDE_W<'_>

Bits 0:7 - TXD drive edge

impl W<u32, Reg<u32, _PROC_CONFIG>>

pub fn proc1_dap_instid(&mut self) -> PROC1_DAP_INSTID_W<'_>

Bits 28:31 - Configure proc1 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP

pub fn proc0_dap_instid(&mut self) -> PROC0_DAP_INSTID_W<'_>

Bits 24:27 - Configure proc0 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP

impl W<u32, Reg<u32, _PROC_IN_SYNC_BYPASS>>

pub fn proc_in_sync_bypass(&mut self) -> PROC_IN_SYNC_BYPASS_W<'_>

Bits 0:29

impl W<u32, Reg<u32, _PROC_IN_SYNC_BYPASS_HI>>

pub fn proc_in_sync_bypass_hi(&mut self) -> PROC_IN_SYNC_BYPASS_HI_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _DBGFORCE>>

pub fn proc1_attach(&mut self) -> PROC1_ATTACH_W<'_>

Bit 7 - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.

pub fn proc1_swclk(&mut self) -> PROC1_SWCLK_W<'_>

Bit 6 - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set

pub fn proc1_swdi(&mut self) -> PROC1_SWDI_W<'_>

Bit 5 - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set

pub fn proc0_attach(&mut self) -> PROC0_ATTACH_W<'_>

Bit 3 - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.

pub fn proc0_swclk(&mut self) -> PROC0_SWCLK_W<'_>

Bit 2 - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set

pub fn proc0_swdi(&mut self) -> PROC0_SWDI_W<'_>

Bit 1 - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set

impl W<u32, Reg<u32, _MEMPOWERDOWN>>

pub fn rom(&mut self) -> ROM_W<'_>

Bit 7

pub fn usb(&mut self) -> USB_W<'_>

Bit 6

pub fn sram5(&mut self) -> SRAM5_W<'_>

Bit 5

pub fn sram4(&mut self) -> SRAM4_W<'_>

Bit 4

pub fn sram3(&mut self) -> SRAM3_W<'_>

Bit 3

pub fn sram2(&mut self) -> SRAM2_W<'_>

Bit 2

pub fn sram1(&mut self) -> SRAM1_W<'_>

Bit 1

pub fn sram0(&mut self) -> SRAM0_W<'_>

Bit 0

impl W<u32, Reg<u32, _CLK_GPOUT0_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn dc50(&mut self) -> DC50_W<'_>

Bit 12 - Enables duty cycle correction for odd divisors

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_GPOUT0_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional component of the divisor

impl W<u32, Reg<u32, _CLK_GPOUT1_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn dc50(&mut self) -> DC50_W<'_>

Bit 12 - Enables duty cycle correction for odd divisors

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_GPOUT1_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional component of the divisor

impl W<u32, Reg<u32, _CLK_GPOUT2_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn dc50(&mut self) -> DC50_W<'_>

Bit 12 - Enables duty cycle correction for odd divisors

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_GPOUT2_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional component of the divisor

impl W<u32, Reg<u32, _CLK_GPOUT3_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn dc50(&mut self) -> DC50_W<'_>

Bit 12 - Enables duty cycle correction for odd divisors

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_GPOUT3_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional component of the divisor

impl W<u32, Reg<u32, _CLK_REF_CTRL>>

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:6 - Selects the auxiliary clock source, will glitch when switching

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly

impl W<u32, Reg<u32, _CLK_REF_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16

impl W<u32, Reg<u32, _CLK_SYS_CTRL>>

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

pub fn src(&mut self) -> SRC_W<'_>

Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly

impl W<u32, Reg<u32, _CLK_SYS_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional component of the divisor

impl W<u32, Reg<u32, _CLK_PERI_CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_USB_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_USB_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16

impl W<u32, Reg<u32, _CLK_ADC_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_ADC_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16

impl W<u32, Reg<u32, _CLK_RTC_CTRL>>

pub fn nudge(&mut self) -> NUDGE_W<'_>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 11 - Starts and stops the clock generator cleanly

pub fn kill(&mut self) -> KILL_W<'_>

Bit 10 - Asynchronously kills the clock generator

pub fn auxsrc(&mut self) -> AUXSRC_W<'_>

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

impl W<u32, Reg<u32, _CLK_RTC_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional component of the divisor

impl W<u32, Reg<u32, _CLK_SYS_RESUS_CTRL>>

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 16 - For clearing the resus after the fault that triggered it has been corrected

pub fn frce(&mut self) -> FRCE_W<'_>

Bit 12 - Force a resus, for test purposes only

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 8 - Enable resus

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:7 - This is expressed as a number of clk_ref cycles\n and must be >= 2x clk_ref_freq/min_clk_tst_freq

impl W<u32, Reg<u32, _FC0_REF_KHZ>>

pub fn fc0_ref_khz(&mut self) -> FC0_REF_KHZ_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _FC0_MIN_KHZ>>

pub fn fc0_min_khz(&mut self) -> FC0_MIN_KHZ_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _FC0_MAX_KHZ>>

pub fn fc0_max_khz(&mut self) -> FC0_MAX_KHZ_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _FC0_DELAY>>

pub fn fc0_delay(&mut self) -> FC0_DELAY_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _FC0_INTERVAL>>

pub fn fc0_interval(&mut self) -> FC0_INTERVAL_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _FC0_SRC>>

pub fn fc0_src(&mut self) -> FC0_SRC_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _WAKE_EN0>>

pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<'_>

Bit 31

pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<'_>

Bit 30

pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<'_>

Bit 29

pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<'_>

Bit 28

pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<'_>

Bit 27

pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<'_>

Bit 26

pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<'_>

Bit 25

pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<'_>

Bit 24

pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<'_>

Bit 23

pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W<'_>

Bit 22

pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W<'_>

Bit 21

pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<'_>

Bit 20

pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<'_>

Bit 19

pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<'_>

Bit 18

pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<'_>

Bit 17

pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<'_>

Bit 16

pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<'_>

Bit 15

pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<'_>

Bit 14

pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<'_>

Bit 13

pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<'_>

Bit 12

pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<'_>

Bit 11

pub fn clk_sys_vreg_and_chip_reset(
    &mut self
) -> CLK_SYS_VREG_AND_CHIP_RESET_W<'_>

Bit 10

pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<'_>

Bit 9

pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<'_>

Bit 8

pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<'_>

Bit 7

pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<'_>

Bit 6

pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<'_>

Bit 5

pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<'_>

Bit 4

pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<'_>

Bit 3

pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<'_>

Bit 2

pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W<'_>

Bit 1

pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<'_>

Bit 0

impl W<u32, Reg<u32, _WAKE_EN1>>

pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<'_>

Bit 14

pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<'_>

Bit 13

pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<'_>

Bit 12

pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W<'_>

Bit 11

pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<'_>

Bit 10

pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<'_>

Bit 9

pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<'_>

Bit 8

pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<'_>

Bit 7

pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<'_>

Bit 6

pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W<'_>

Bit 5

pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<'_>

Bit 4

pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<'_>

Bit 3

pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<'_>

Bit 2

pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<'_>

Bit 1

pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<'_>

Bit 0

impl W<u32, Reg<u32, _SLEEP_EN0>>

pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<'_>

Bit 31

pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<'_>

Bit 30

pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<'_>

Bit 29

pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<'_>

Bit 28

pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<'_>

Bit 27

pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<'_>

Bit 26

pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<'_>

Bit 25

pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<'_>

Bit 24

pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<'_>

Bit 23

pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W<'_>

Bit 22

pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W<'_>

Bit 21

pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<'_>

Bit 20

pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<'_>

Bit 19

pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<'_>

Bit 18

pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<'_>

Bit 17

pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<'_>

Bit 16

pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<'_>

Bit 15

pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<'_>

Bit 14

pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<'_>

Bit 13

pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<'_>

Bit 12

pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<'_>

Bit 11

pub fn clk_sys_vreg_and_chip_reset(
    &mut self
) -> CLK_SYS_VREG_AND_CHIP_RESET_W<'_>

Bit 10

pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<'_>

Bit 9

pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<'_>

Bit 8

pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<'_>

Bit 7

pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<'_>

Bit 6

pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<'_>

Bit 5

pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<'_>

Bit 4

pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<'_>

Bit 3

pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<'_>

Bit 2

pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W<'_>

Bit 1

pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<'_>

Bit 0

impl W<u32, Reg<u32, _SLEEP_EN1>>

pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<'_>

Bit 14

pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<'_>

Bit 13

pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<'_>

Bit 12

pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W<'_>

Bit 11

pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<'_>

Bit 10

pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<'_>

Bit 9

pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<'_>

Bit 8

pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<'_>

Bit 7

pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<'_>

Bit 6

pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W<'_>

Bit 5

pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<'_>

Bit 4

pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<'_>

Bit 3

pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<'_>

Bit 2

pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<'_>

Bit 1

pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTE>>

pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTF>>

pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W<'_>

Bit 0

impl W<u32, Reg<u32, _RESET>>

pub fn usbctrl(&mut self) -> USBCTRL_W<'_>

Bit 24

pub fn uart1(&mut self) -> UART1_W<'_>

Bit 23

pub fn uart0(&mut self) -> UART0_W<'_>

Bit 22

pub fn timer(&mut self) -> TIMER_W<'_>

Bit 21

pub fn tbman(&mut self) -> TBMAN_W<'_>

Bit 20

pub fn sysinfo(&mut self) -> SYSINFO_W<'_>

Bit 19

pub fn syscfg(&mut self) -> SYSCFG_W<'_>

Bit 18

pub fn spi1(&mut self) -> SPI1_W<'_>

Bit 17

pub fn spi0(&mut self) -> SPI0_W<'_>

Bit 16

pub fn rtc(&mut self) -> RTC_W<'_>

Bit 15

pub fn pwm(&mut self) -> PWM_W<'_>

Bit 14

pub fn pll_usb(&mut self) -> PLL_USB_W<'_>

Bit 13

pub fn pll_sys(&mut self) -> PLL_SYS_W<'_>

Bit 12

pub fn pio1(&mut self) -> PIO1_W<'_>

Bit 11

pub fn pio0(&mut self) -> PIO0_W<'_>

Bit 10

pub fn pads_qspi(&mut self) -> PADS_QSPI_W<'_>

Bit 9

pub fn pads_bank0(&mut self) -> PADS_BANK0_W<'_>

Bit 8

pub fn jtag(&mut self) -> JTAG_W<'_>

Bit 7

pub fn io_qspi(&mut self) -> IO_QSPI_W<'_>

Bit 6

pub fn io_bank0(&mut self) -> IO_BANK0_W<'_>

Bit 5

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 4

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 3

pub fn dma(&mut self) -> DMA_W<'_>

Bit 2

pub fn busctrl(&mut self) -> BUSCTRL_W<'_>

Bit 1

pub fn adc(&mut self) -> ADC_W<'_>

Bit 0

impl W<u32, Reg<u32, _WDSEL>>

pub fn usbctrl(&mut self) -> USBCTRL_W<'_>

Bit 24

pub fn uart1(&mut self) -> UART1_W<'_>

Bit 23

pub fn uart0(&mut self) -> UART0_W<'_>

Bit 22

pub fn timer(&mut self) -> TIMER_W<'_>

Bit 21

pub fn tbman(&mut self) -> TBMAN_W<'_>

Bit 20

pub fn sysinfo(&mut self) -> SYSINFO_W<'_>

Bit 19

pub fn syscfg(&mut self) -> SYSCFG_W<'_>

Bit 18

pub fn spi1(&mut self) -> SPI1_W<'_>

Bit 17

pub fn spi0(&mut self) -> SPI0_W<'_>

Bit 16

pub fn rtc(&mut self) -> RTC_W<'_>

Bit 15

pub fn pwm(&mut self) -> PWM_W<'_>

Bit 14

pub fn pll_usb(&mut self) -> PLL_USB_W<'_>

Bit 13

pub fn pll_sys(&mut self) -> PLL_SYS_W<'_>

Bit 12

pub fn pio1(&mut self) -> PIO1_W<'_>

Bit 11

pub fn pio0(&mut self) -> PIO0_W<'_>

Bit 10

pub fn pads_qspi(&mut self) -> PADS_QSPI_W<'_>

Bit 9

pub fn pads_bank0(&mut self) -> PADS_BANK0_W<'_>

Bit 8

pub fn jtag(&mut self) -> JTAG_W<'_>

Bit 7

pub fn io_qspi(&mut self) -> IO_QSPI_W<'_>

Bit 6

pub fn io_bank0(&mut self) -> IO_BANK0_W<'_>

Bit 5

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 4

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 3

pub fn dma(&mut self) -> DMA_W<'_>

Bit 2

pub fn busctrl(&mut self) -> BUSCTRL_W<'_>

Bit 1

pub fn adc(&mut self) -> ADC_W<'_>

Bit 0

impl W<u32, Reg<u32, _FRCE_ON>>

pub fn proc1(&mut self) -> PROC1_W<'_>

Bit 16

pub fn proc0(&mut self) -> PROC0_W<'_>

Bit 15

pub fn sio(&mut self) -> SIO_W<'_>

Bit 14

pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<'_>

Bit 13

pub fn xip(&mut self) -> XIP_W<'_>

Bit 12

pub fn sram5(&mut self) -> SRAM5_W<'_>

Bit 11

pub fn sram4(&mut self) -> SRAM4_W<'_>

Bit 10

pub fn sram3(&mut self) -> SRAM3_W<'_>

Bit 9

pub fn sram2(&mut self) -> SRAM2_W<'_>

Bit 8

pub fn sram1(&mut self) -> SRAM1_W<'_>

Bit 7

pub fn sram0(&mut self) -> SRAM0_W<'_>

Bit 6

pub fn rom(&mut self) -> ROM_W<'_>

Bit 5

pub fn busfabric(&mut self) -> BUSFABRIC_W<'_>

Bit 4

pub fn resets(&mut self) -> RESETS_W<'_>

Bit 3

pub fn clocks(&mut self) -> CLOCKS_W<'_>

Bit 2

pub fn xosc(&mut self) -> XOSC_W<'_>

Bit 1

pub fn rosc(&mut self) -> ROSC_W<'_>

Bit 0

impl W<u32, Reg<u32, _FRCE_OFF>>

pub fn proc1(&mut self) -> PROC1_W<'_>

Bit 16

pub fn proc0(&mut self) -> PROC0_W<'_>

Bit 15

pub fn sio(&mut self) -> SIO_W<'_>

Bit 14

pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<'_>

Bit 13

pub fn xip(&mut self) -> XIP_W<'_>

Bit 12

pub fn sram5(&mut self) -> SRAM5_W<'_>

Bit 11

pub fn sram4(&mut self) -> SRAM4_W<'_>

Bit 10

pub fn sram3(&mut self) -> SRAM3_W<'_>

Bit 9

pub fn sram2(&mut self) -> SRAM2_W<'_>

Bit 8

pub fn sram1(&mut self) -> SRAM1_W<'_>

Bit 7

pub fn sram0(&mut self) -> SRAM0_W<'_>

Bit 6

pub fn rom(&mut self) -> ROM_W<'_>

Bit 5

pub fn busfabric(&mut self) -> BUSFABRIC_W<'_>

Bit 4

pub fn resets(&mut self) -> RESETS_W<'_>

Bit 3

pub fn clocks(&mut self) -> CLOCKS_W<'_>

Bit 2

pub fn xosc(&mut self) -> XOSC_W<'_>

Bit 1

pub fn rosc(&mut self) -> ROSC_W<'_>

Bit 0

impl W<u32, Reg<u32, _WDSEL>>

pub fn proc1(&mut self) -> PROC1_W<'_>

Bit 16

pub fn proc0(&mut self) -> PROC0_W<'_>

Bit 15

pub fn sio(&mut self) -> SIO_W<'_>

Bit 14

pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<'_>

Bit 13

pub fn xip(&mut self) -> XIP_W<'_>

Bit 12

pub fn sram5(&mut self) -> SRAM5_W<'_>

Bit 11

pub fn sram4(&mut self) -> SRAM4_W<'_>

Bit 10

pub fn sram3(&mut self) -> SRAM3_W<'_>

Bit 9

pub fn sram2(&mut self) -> SRAM2_W<'_>

Bit 8

pub fn sram1(&mut self) -> SRAM1_W<'_>

Bit 7

pub fn sram0(&mut self) -> SRAM0_W<'_>

Bit 6

pub fn rom(&mut self) -> ROM_W<'_>

Bit 5

pub fn busfabric(&mut self) -> BUSFABRIC_W<'_>

Bit 4

pub fn resets(&mut self) -> RESETS_W<'_>

Bit 3

pub fn clocks(&mut self) -> CLOCKS_W<'_>

Bit 2

pub fn xosc(&mut self) -> XOSC_W<'_>

Bit 1

pub fn rosc(&mut self) -> ROSC_W<'_>

Bit 0

impl W<u32, Reg<u32, _GPIO0_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO1_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO2_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO3_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO4_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO5_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO6_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO7_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO8_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO9_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO10_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO11_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO12_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO13_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO14_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO15_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO16_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO17_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO18_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO19_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO20_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO21_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO22_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO23_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO24_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO25_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO26_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO27_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO28_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO29_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _INTR0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

impl W<u32, Reg<u32, _INTR1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

impl W<u32, Reg<u32, _INTR2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

impl W<u32, Reg<u32, _INTR3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

impl W<u32, Reg<u32, _PROC0_INTE0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTE1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio15_level_high(&mut self) -> GPIO15_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio15_level_low(&mut self) -> GPIO15_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio14_level_high(&mut self) -> GPIO14_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio14_level_low(&mut self) -> GPIO14_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio13_level_high(&mut self) -> GPIO13_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio13_level_low(&mut self) -> GPIO13_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio12_level_high(&mut self) -> GPIO12_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio12_level_low(&mut self) -> GPIO12_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio11_level_high(&mut self) -> GPIO11_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio11_level_low(&mut self) -> GPIO11_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio10_level_high(&mut self) -> GPIO10_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio10_level_low(&mut self) -> GPIO10_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio9_level_high(&mut self) -> GPIO9_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio9_level_low(&mut self) -> GPIO9_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

pub fn gpio8_level_high(&mut self) -> GPIO8_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio8_level_low(&mut self) -> GPIO8_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTE2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio23_level_high(&mut self) -> GPIO23_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio23_level_low(&mut self) -> GPIO23_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio22_level_high(&mut self) -> GPIO22_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio22_level_low(&mut self) -> GPIO22_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio21_level_high(&mut self) -> GPIO21_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio21_level_low(&mut self) -> GPIO21_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio20_level_high(&mut self) -> GPIO20_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio20_level_low(&mut self) -> GPIO20_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio19_level_high(&mut self) -> GPIO19_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio19_level_low(&mut self) -> GPIO19_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio18_level_high(&mut self) -> GPIO18_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio18_level_low(&mut self) -> GPIO18_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio17_level_high(&mut self) -> GPIO17_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio17_level_low(&mut self) -> GPIO17_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

pub fn gpio16_level_high(&mut self) -> GPIO16_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio16_level_low(&mut self) -> GPIO16_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTE3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio29_level_high(&mut self) -> GPIO29_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio29_level_low(&mut self) -> GPIO29_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio28_level_high(&mut self) -> GPIO28_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio28_level_low(&mut self) -> GPIO28_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio27_level_high(&mut self) -> GPIO27_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio27_level_low(&mut self) -> GPIO27_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio26_level_high(&mut self) -> GPIO26_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio26_level_low(&mut self) -> GPIO26_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio25_level_high(&mut self) -> GPIO25_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio25_level_low(&mut self) -> GPIO25_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

pub fn gpio24_level_high(&mut self) -> GPIO24_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio24_level_low(&mut self) -> GPIO24_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTF0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTF1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio15_level_high(&mut self) -> GPIO15_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio15_level_low(&mut self) -> GPIO15_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio14_level_high(&mut self) -> GPIO14_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio14_level_low(&mut self) -> GPIO14_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio13_level_high(&mut self) -> GPIO13_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio13_level_low(&mut self) -> GPIO13_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio12_level_high(&mut self) -> GPIO12_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio12_level_low(&mut self) -> GPIO12_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio11_level_high(&mut self) -> GPIO11_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio11_level_low(&mut self) -> GPIO11_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio10_level_high(&mut self) -> GPIO10_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio10_level_low(&mut self) -> GPIO10_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio9_level_high(&mut self) -> GPIO9_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio9_level_low(&mut self) -> GPIO9_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

pub fn gpio8_level_high(&mut self) -> GPIO8_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio8_level_low(&mut self) -> GPIO8_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTF2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio23_level_high(&mut self) -> GPIO23_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio23_level_low(&mut self) -> GPIO23_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio22_level_high(&mut self) -> GPIO22_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio22_level_low(&mut self) -> GPIO22_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio21_level_high(&mut self) -> GPIO21_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio21_level_low(&mut self) -> GPIO21_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio20_level_high(&mut self) -> GPIO20_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio20_level_low(&mut self) -> GPIO20_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio19_level_high(&mut self) -> GPIO19_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio19_level_low(&mut self) -> GPIO19_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio18_level_high(&mut self) -> GPIO18_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio18_level_low(&mut self) -> GPIO18_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio17_level_high(&mut self) -> GPIO17_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio17_level_low(&mut self) -> GPIO17_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

pub fn gpio16_level_high(&mut self) -> GPIO16_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio16_level_low(&mut self) -> GPIO16_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTF3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio29_level_high(&mut self) -> GPIO29_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio29_level_low(&mut self) -> GPIO29_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio28_level_high(&mut self) -> GPIO28_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio28_level_low(&mut self) -> GPIO28_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio27_level_high(&mut self) -> GPIO27_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio27_level_low(&mut self) -> GPIO27_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio26_level_high(&mut self) -> GPIO26_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio26_level_low(&mut self) -> GPIO26_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio25_level_high(&mut self) -> GPIO25_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio25_level_low(&mut self) -> GPIO25_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

pub fn gpio24_level_high(&mut self) -> GPIO24_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio24_level_low(&mut self) -> GPIO24_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTE0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTE1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio15_level_high(&mut self) -> GPIO15_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio15_level_low(&mut self) -> GPIO15_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio14_level_high(&mut self) -> GPIO14_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio14_level_low(&mut self) -> GPIO14_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio13_level_high(&mut self) -> GPIO13_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio13_level_low(&mut self) -> GPIO13_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio12_level_high(&mut self) -> GPIO12_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio12_level_low(&mut self) -> GPIO12_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio11_level_high(&mut self) -> GPIO11_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio11_level_low(&mut self) -> GPIO11_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio10_level_high(&mut self) -> GPIO10_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio10_level_low(&mut self) -> GPIO10_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio9_level_high(&mut self) -> GPIO9_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio9_level_low(&mut self) -> GPIO9_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

pub fn gpio8_level_high(&mut self) -> GPIO8_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio8_level_low(&mut self) -> GPIO8_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTE2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio23_level_high(&mut self) -> GPIO23_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio23_level_low(&mut self) -> GPIO23_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio22_level_high(&mut self) -> GPIO22_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio22_level_low(&mut self) -> GPIO22_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio21_level_high(&mut self) -> GPIO21_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio21_level_low(&mut self) -> GPIO21_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio20_level_high(&mut self) -> GPIO20_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio20_level_low(&mut self) -> GPIO20_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio19_level_high(&mut self) -> GPIO19_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio19_level_low(&mut self) -> GPIO19_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio18_level_high(&mut self) -> GPIO18_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio18_level_low(&mut self) -> GPIO18_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio17_level_high(&mut self) -> GPIO17_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio17_level_low(&mut self) -> GPIO17_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

pub fn gpio16_level_high(&mut self) -> GPIO16_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio16_level_low(&mut self) -> GPIO16_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTE3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio29_level_high(&mut self) -> GPIO29_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio29_level_low(&mut self) -> GPIO29_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio28_level_high(&mut self) -> GPIO28_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio28_level_low(&mut self) -> GPIO28_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio27_level_high(&mut self) -> GPIO27_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio27_level_low(&mut self) -> GPIO27_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio26_level_high(&mut self) -> GPIO26_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio26_level_low(&mut self) -> GPIO26_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio25_level_high(&mut self) -> GPIO25_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio25_level_low(&mut self) -> GPIO25_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

pub fn gpio24_level_high(&mut self) -> GPIO24_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio24_level_low(&mut self) -> GPIO24_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTF0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTF1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio15_level_high(&mut self) -> GPIO15_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio15_level_low(&mut self) -> GPIO15_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio14_level_high(&mut self) -> GPIO14_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio14_level_low(&mut self) -> GPIO14_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio13_level_high(&mut self) -> GPIO13_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio13_level_low(&mut self) -> GPIO13_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio12_level_high(&mut self) -> GPIO12_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio12_level_low(&mut self) -> GPIO12_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio11_level_high(&mut self) -> GPIO11_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio11_level_low(&mut self) -> GPIO11_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio10_level_high(&mut self) -> GPIO10_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio10_level_low(&mut self) -> GPIO10_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio9_level_high(&mut self) -> GPIO9_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio9_level_low(&mut self) -> GPIO9_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

pub fn gpio8_level_high(&mut self) -> GPIO8_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio8_level_low(&mut self) -> GPIO8_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTF2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio23_level_high(&mut self) -> GPIO23_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio23_level_low(&mut self) -> GPIO23_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio22_level_high(&mut self) -> GPIO22_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio22_level_low(&mut self) -> GPIO22_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio21_level_high(&mut self) -> GPIO21_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio21_level_low(&mut self) -> GPIO21_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio20_level_high(&mut self) -> GPIO20_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio20_level_low(&mut self) -> GPIO20_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio19_level_high(&mut self) -> GPIO19_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio19_level_low(&mut self) -> GPIO19_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio18_level_high(&mut self) -> GPIO18_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio18_level_low(&mut self) -> GPIO18_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio17_level_high(&mut self) -> GPIO17_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio17_level_low(&mut self) -> GPIO17_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

pub fn gpio16_level_high(&mut self) -> GPIO16_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio16_level_low(&mut self) -> GPIO16_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTF3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio29_level_high(&mut self) -> GPIO29_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio29_level_low(&mut self) -> GPIO29_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio28_level_high(&mut self) -> GPIO28_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio28_level_low(&mut self) -> GPIO28_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio27_level_high(&mut self) -> GPIO27_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio27_level_low(&mut self) -> GPIO27_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio26_level_high(&mut self) -> GPIO26_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio26_level_low(&mut self) -> GPIO26_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio25_level_high(&mut self) -> GPIO25_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio25_level_low(&mut self) -> GPIO25_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

pub fn gpio24_level_high(&mut self) -> GPIO24_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio24_level_low(&mut self) -> GPIO24_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTE0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTE1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio15_level_high(&mut self) -> GPIO15_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio15_level_low(&mut self) -> GPIO15_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio14_level_high(&mut self) -> GPIO14_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio14_level_low(&mut self) -> GPIO14_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio13_level_high(&mut self) -> GPIO13_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio13_level_low(&mut self) -> GPIO13_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio12_level_high(&mut self) -> GPIO12_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio12_level_low(&mut self) -> GPIO12_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio11_level_high(&mut self) -> GPIO11_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio11_level_low(&mut self) -> GPIO11_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio10_level_high(&mut self) -> GPIO10_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio10_level_low(&mut self) -> GPIO10_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio9_level_high(&mut self) -> GPIO9_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio9_level_low(&mut self) -> GPIO9_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

pub fn gpio8_level_high(&mut self) -> GPIO8_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio8_level_low(&mut self) -> GPIO8_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTE2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio23_level_high(&mut self) -> GPIO23_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio23_level_low(&mut self) -> GPIO23_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio22_level_high(&mut self) -> GPIO22_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio22_level_low(&mut self) -> GPIO22_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio21_level_high(&mut self) -> GPIO21_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio21_level_low(&mut self) -> GPIO21_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio20_level_high(&mut self) -> GPIO20_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio20_level_low(&mut self) -> GPIO20_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio19_level_high(&mut self) -> GPIO19_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio19_level_low(&mut self) -> GPIO19_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio18_level_high(&mut self) -> GPIO18_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio18_level_low(&mut self) -> GPIO18_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio17_level_high(&mut self) -> GPIO17_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio17_level_low(&mut self) -> GPIO17_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

pub fn gpio16_level_high(&mut self) -> GPIO16_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio16_level_low(&mut self) -> GPIO16_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTE3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio29_level_high(&mut self) -> GPIO29_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio29_level_low(&mut self) -> GPIO29_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio28_level_high(&mut self) -> GPIO28_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio28_level_low(&mut self) -> GPIO28_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio27_level_high(&mut self) -> GPIO27_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio27_level_low(&mut self) -> GPIO27_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio26_level_high(&mut self) -> GPIO26_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio26_level_low(&mut self) -> GPIO26_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio25_level_high(&mut self) -> GPIO25_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio25_level_low(&mut self) -> GPIO25_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

pub fn gpio24_level_high(&mut self) -> GPIO24_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio24_level_low(&mut self) -> GPIO24_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTF0>>

pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<'_>

Bit 30

pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<'_>

Bit 26

pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<'_>

Bit 22

pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<'_>

Bit 18

pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<'_>

Bit 14

pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<'_>

Bit 10

pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<'_>

Bit 6

pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<'_>

Bit 2

pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTF1>>

pub fn gpio15_edge_high(&mut self) -> GPIO15_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio15_edge_low(&mut self) -> GPIO15_EDGE_LOW_W<'_>

Bit 30

pub fn gpio15_level_high(&mut self) -> GPIO15_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio15_level_low(&mut self) -> GPIO15_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio14_edge_high(&mut self) -> GPIO14_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio14_edge_low(&mut self) -> GPIO14_EDGE_LOW_W<'_>

Bit 26

pub fn gpio14_level_high(&mut self) -> GPIO14_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio14_level_low(&mut self) -> GPIO14_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio13_edge_high(&mut self) -> GPIO13_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio13_edge_low(&mut self) -> GPIO13_EDGE_LOW_W<'_>

Bit 22

pub fn gpio13_level_high(&mut self) -> GPIO13_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio13_level_low(&mut self) -> GPIO13_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio12_edge_high(&mut self) -> GPIO12_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio12_edge_low(&mut self) -> GPIO12_EDGE_LOW_W<'_>

Bit 18

pub fn gpio12_level_high(&mut self) -> GPIO12_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio12_level_low(&mut self) -> GPIO12_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio11_edge_high(&mut self) -> GPIO11_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio11_edge_low(&mut self) -> GPIO11_EDGE_LOW_W<'_>

Bit 14

pub fn gpio11_level_high(&mut self) -> GPIO11_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio11_level_low(&mut self) -> GPIO11_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio10_edge_high(&mut self) -> GPIO10_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio10_edge_low(&mut self) -> GPIO10_EDGE_LOW_W<'_>

Bit 10

pub fn gpio10_level_high(&mut self) -> GPIO10_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio10_level_low(&mut self) -> GPIO10_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio9_edge_high(&mut self) -> GPIO9_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio9_edge_low(&mut self) -> GPIO9_EDGE_LOW_W<'_>

Bit 6

pub fn gpio9_level_high(&mut self) -> GPIO9_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio9_level_low(&mut self) -> GPIO9_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio8_edge_high(&mut self) -> GPIO8_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio8_edge_low(&mut self) -> GPIO8_EDGE_LOW_W<'_>

Bit 2

pub fn gpio8_level_high(&mut self) -> GPIO8_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio8_level_low(&mut self) -> GPIO8_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTF2>>

pub fn gpio23_edge_high(&mut self) -> GPIO23_EDGE_HIGH_W<'_>

Bit 31

pub fn gpio23_edge_low(&mut self) -> GPIO23_EDGE_LOW_W<'_>

Bit 30

pub fn gpio23_level_high(&mut self) -> GPIO23_LEVEL_HIGH_W<'_>

Bit 29

pub fn gpio23_level_low(&mut self) -> GPIO23_LEVEL_LOW_W<'_>

Bit 28

pub fn gpio22_edge_high(&mut self) -> GPIO22_EDGE_HIGH_W<'_>

Bit 27

pub fn gpio22_edge_low(&mut self) -> GPIO22_EDGE_LOW_W<'_>

Bit 26

pub fn gpio22_level_high(&mut self) -> GPIO22_LEVEL_HIGH_W<'_>

Bit 25

pub fn gpio22_level_low(&mut self) -> GPIO22_LEVEL_LOW_W<'_>

Bit 24

pub fn gpio21_edge_high(&mut self) -> GPIO21_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio21_edge_low(&mut self) -> GPIO21_EDGE_LOW_W<'_>

Bit 22

pub fn gpio21_level_high(&mut self) -> GPIO21_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio21_level_low(&mut self) -> GPIO21_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio20_edge_high(&mut self) -> GPIO20_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio20_edge_low(&mut self) -> GPIO20_EDGE_LOW_W<'_>

Bit 18

pub fn gpio20_level_high(&mut self) -> GPIO20_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio20_level_low(&mut self) -> GPIO20_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio19_edge_high(&mut self) -> GPIO19_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio19_edge_low(&mut self) -> GPIO19_EDGE_LOW_W<'_>

Bit 14

pub fn gpio19_level_high(&mut self) -> GPIO19_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio19_level_low(&mut self) -> GPIO19_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio18_edge_high(&mut self) -> GPIO18_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio18_edge_low(&mut self) -> GPIO18_EDGE_LOW_W<'_>

Bit 10

pub fn gpio18_level_high(&mut self) -> GPIO18_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio18_level_low(&mut self) -> GPIO18_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio17_edge_high(&mut self) -> GPIO17_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio17_edge_low(&mut self) -> GPIO17_EDGE_LOW_W<'_>

Bit 6

pub fn gpio17_level_high(&mut self) -> GPIO17_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio17_level_low(&mut self) -> GPIO17_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio16_edge_high(&mut self) -> GPIO16_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio16_edge_low(&mut self) -> GPIO16_EDGE_LOW_W<'_>

Bit 2

pub fn gpio16_level_high(&mut self) -> GPIO16_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio16_level_low(&mut self) -> GPIO16_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTF3>>

pub fn gpio29_edge_high(&mut self) -> GPIO29_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio29_edge_low(&mut self) -> GPIO29_EDGE_LOW_W<'_>

Bit 22

pub fn gpio29_level_high(&mut self) -> GPIO29_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio29_level_low(&mut self) -> GPIO29_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio28_edge_high(&mut self) -> GPIO28_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio28_edge_low(&mut self) -> GPIO28_EDGE_LOW_W<'_>

Bit 18

pub fn gpio28_level_high(&mut self) -> GPIO28_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio28_level_low(&mut self) -> GPIO28_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio27_edge_high(&mut self) -> GPIO27_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio27_edge_low(&mut self) -> GPIO27_EDGE_LOW_W<'_>

Bit 14

pub fn gpio27_level_high(&mut self) -> GPIO27_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio27_level_low(&mut self) -> GPIO27_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio26_edge_high(&mut self) -> GPIO26_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio26_edge_low(&mut self) -> GPIO26_EDGE_LOW_W<'_>

Bit 10

pub fn gpio26_level_high(&mut self) -> GPIO26_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio26_level_low(&mut self) -> GPIO26_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio25_edge_high(&mut self) -> GPIO25_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio25_edge_low(&mut self) -> GPIO25_EDGE_LOW_W<'_>

Bit 6

pub fn gpio25_level_high(&mut self) -> GPIO25_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio25_level_low(&mut self) -> GPIO25_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio24_edge_high(&mut self) -> GPIO24_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio24_edge_low(&mut self) -> GPIO24_EDGE_LOW_W<'_>

Bit 2

pub fn gpio24_level_high(&mut self) -> GPIO24_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio24_level_low(&mut self) -> GPIO24_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _GPIO_QSPI_SCLK_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO_QSPI_SS_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO_QSPI_SD0_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO_QSPI_SD1_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO_QSPI_SD2_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _GPIO_QSPI_SD3_CTRL>>

pub fn irqover(&mut self) -> IRQOVER_W<'_>

Bits 28:29

pub fn inover(&mut self) -> INOVER_W<'_>

Bits 16:17

pub fn oeover(&mut self) -> OEOVER_W<'_>

Bits 12:13

pub fn outover(&mut self) -> OUTOVER_W<'_>

Bits 8:9

pub fn funcsel(&mut self) -> FUNCSEL_W<'_>

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

impl W<u32, Reg<u32, _INTR>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

impl W<u32, Reg<u32, _PROC0_INTE>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC0_INTF>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTE>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _PROC1_INTF>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTE>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DORMANT_WAKE_INTF>>

pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<'_>

Bit 23

pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<'_>

Bit 22

pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<'_>

Bit 21

pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<'_>

Bit 20

pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<'_>

Bit 19

pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<'_>

Bit 18

pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<'_>

Bit 17

pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<'_>

Bit 16

pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<'_>

Bit 15

pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<'_>

Bit 14

pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<'_>

Bit 13

pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<'_>

Bit 12

pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<'_>

Bit 11

pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<'_>

Bit 10

pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<'_>

Bit 9

pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<'_>

Bit 8

pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<'_>

Bit 7

pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<'_>

Bit 6

pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<'_>

Bit 5

pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<'_>

Bit 4

pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<'_>

Bit 3

pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<'_>

Bit 2

pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'_>

Bit 1

pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<'_>

Bit 0

impl W<u32, Reg<u32, _VOLTAGE_SELECT>>

pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W<'_>

Bit 0

impl W<u32, Reg<u32, _GPIO0>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO1>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO2>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO3>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO4>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO5>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO6>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO7>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO8>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO9>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO10>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO11>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO12>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO13>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO14>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO15>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO16>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO17>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO18>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO19>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO20>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO21>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO22>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO23>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO24>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO25>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO26>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO27>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO28>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO29>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _SWCLK>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _SWD>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _VOLTAGE_SELECT>>

pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W<'_>

Bit 0

impl W<u32, Reg<u32, _GPIO_QSPI_SCLK>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO_QSPI_SD0>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO_QSPI_SD1>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO_QSPI_SD2>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO_QSPI_SD3>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _GPIO_QSPI_SS>>

pub fn od(&mut self) -> OD_W<'_>

Bit 7 - Output disable. Has priority over output enable from peripherals

pub fn ie(&mut self) -> IE_W<'_>

Bit 6 - Input enable

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 4:5 - Drive strength.

pub fn pue(&mut self) -> PUE_W<'_>

Bit 3 - Pull up enable

pub fn pde(&mut self) -> PDE_W<'_>

Bit 2 - Pull down enable

pub fn schmitt(&mut self) -> SCHMITT_W<'_>

Bit 1 - Enable schmitt trigger

pub fn slewfast(&mut self) -> SLEWFAST_W<'_>

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.

pub fn freq_range(&mut self) -> FREQ_RANGE_W<'_>

Bits 0:11 - Frequency range. This resets to 0xAA0 and cannot be changed.

impl W<u32, Reg<u32, _STATUS>>

pub fn badwrite(&mut self) -> BADWRITE_W<'_>

Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT

impl W<u32, Reg<u32, _STARTUP>>

pub fn x4(&mut self) -> X4_W<'_>

Bit 20 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 0:13 - in multiples of 256*xtal_period

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CS>>

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

pub fn refdiv(&mut self) -> REFDIV_W<'_>

Bits 0:5 - Divides the PLL input reference clock.\n Behaviour is undefined for div=0.\n PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

impl W<u32, Reg<u32, _PWR>>

pub fn vcopd(&mut self) -> VCOPD_W<'_>

Bit 5 - PLL VCO powerdown\n To save power set high when PLL output not required or bypass=1.

pub fn postdivpd(&mut self) -> POSTDIVPD_W<'_>

Bit 3 - PLL post divider powerdown\n To save power set high when PLL output not required or bypass=1.

pub fn dsmpd(&mut self) -> DSMPD_W<'_>

Bit 2 - PLL DSM powerdown\n Nothing is achieved by setting this low.

pub fn pd(&mut self) -> PD_W<'_>

Bit 0 - PLL powerdown\n To save power set high when PLL output not required.

impl W<u32, Reg<u32, _FBDIV_INT>>

pub fn fbdiv_int(&mut self) -> FBDIV_INT_W<'_>

Bits 0:11 - see ctrl reg description for constraints

impl W<u32, Reg<u32, _PRIM>>

pub fn postdiv1(&mut self) -> POSTDIV1_W<'_>

Bits 16:18 - divide by 1-7

pub fn postdiv2(&mut self) -> POSTDIV2_W<'_>

Bits 12:14 - divide by 1-7

impl W<u32, Reg<u32, _BUS_PRIORITY>>

pub fn dma_w(&mut self) -> DMA_W_W<'_>

Bit 12 - 0 - low priority, 1 - high priority

pub fn dma_r(&mut self) -> DMA_R_W<'_>

Bit 8 - 0 - low priority, 1 - high priority

pub fn proc1(&mut self) -> PROC1_W<'_>

Bit 4 - 0 - low priority, 1 - high priority

pub fn proc0(&mut self) -> PROC0_W<'_>

Bit 0 - 0 - low priority, 1 - high priority

impl W<u32, Reg<u32, _PERFCTR0>>

pub fn perfctr0(&mut self) -> PERFCTR0_W<'_>

Bits 0:23 - Busfabric saturating performance counter 0\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL0

impl W<u32, Reg<u32, _PERFSEL0>>

pub fn perfsel0(&mut self) -> PERFSEL0_W<'_>

Bits 0:4 - Select a performance event for PERFCTR0

impl W<u32, Reg<u32, _PERFCTR1>>

pub fn perfctr1(&mut self) -> PERFCTR1_W<'_>

Bits 0:23 - Busfabric saturating performance counter 1\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL1

impl W<u32, Reg<u32, _PERFSEL1>>

pub fn perfsel1(&mut self) -> PERFSEL1_W<'_>

Bits 0:4 - Select a performance event for PERFCTR1

impl W<u32, Reg<u32, _PERFCTR2>>

pub fn perfctr2(&mut self) -> PERFCTR2_W<'_>

Bits 0:23 - Busfabric saturating performance counter 2\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL2

impl W<u32, Reg<u32, _PERFSEL2>>

pub fn perfsel2(&mut self) -> PERFSEL2_W<'_>

Bits 0:4 - Select a performance event for PERFCTR2

impl W<u32, Reg<u32, _PERFCTR3>>

pub fn perfctr3(&mut self) -> PERFCTR3_W<'_>

Bits 0:23 - Busfabric saturating performance counter 3\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL3

impl W<u32, Reg<u32, _PERFSEL3>>

pub fn perfsel3(&mut self) -> PERFSEL3_W<'_>

Bits 0:4 - Select a performance event for PERFCTR3

impl W<u32, Reg<u32, _UARTDR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - Receive (read) data character. Transmit (write) data character.

impl W<u32, Reg<u32, _UARTRSR>>

pub fn oe(&mut self) -> OE_W<'_>

Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

pub fn be(&mut self) -> BE_W<'_>

Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

pub fn pe(&mut self) -> PE_W<'_>

Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

pub fn fe(&mut self) -> FE_W<'_>

Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

impl W<u32, Reg<u32, _UARTILPR>>

pub fn ilpdvsr(&mut self) -> ILPDVSR_W<'_>

Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset.

impl W<u32, Reg<u32, _UARTIBRD>>

pub fn baud_divint(&mut self) -> BAUD_DIVINT_W<'_>

Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset.

impl W<u32, Reg<u32, _UARTFBRD>>

pub fn baud_divfrac(&mut self) -> BAUD_DIVFRAC_W<'_>

Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset.

impl W<u32, Reg<u32, _UARTLCR_H>>

pub fn sps(&mut self) -> SPS_W<'_>

Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

pub fn wlen(&mut self) -> WLEN_W<'_>

Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.

pub fn fen(&mut self) -> FEN_W<'_>

Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

pub fn stp2(&mut self) -> STP2_W<'_>

Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

pub fn eps(&mut self) -> EPS_W<'_>

Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

pub fn pen(&mut self) -> PEN_W<'_>

Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

pub fn brk(&mut self) -> BRK_W<'_>

Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

impl W<u32, Reg<u32, _UARTCR>>

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.

pub fn rtsen(&mut self) -> RTSEN_W<'_>

Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.

pub fn out2(&mut self) -> OUT2_W<'_>

Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).

pub fn out1(&mut self) -> OUT1_W<'_>

Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).

pub fn rts(&mut self) -> RTS_W<'_>

Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.

pub fn dtr(&mut self) -> DTR_W<'_>

Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.

pub fn rxe(&mut self) -> RXE_W<'_>

Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.

pub fn txe(&mut self) -> TXE_W<'_>

Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.

pub fn lbe(&mut self) -> LBE_W<'_>

Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.

pub fn sirlp(&mut self) -> SIRLP_W<'_>

Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.

pub fn siren(&mut self) -> SIREN_W<'_>

Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.

pub fn uarten(&mut self) -> UARTEN_W<'_>

Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.

impl W<u32, Reg<u32, _UARTIFLS>>

pub fn rxiflsel(&mut self) -> RXIFLSEL_W<'_>

Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.

pub fn txiflsel(&mut self) -> TXIFLSEL_W<'_>

Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.

impl W<u32, Reg<u32, _UARTIMSC>>

pub fn oeim(&mut self) -> OEIM_W<'_>

Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.

pub fn beim(&mut self) -> BEIM_W<'_>

Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.

pub fn peim(&mut self) -> PEIM_W<'_>

Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.

pub fn feim(&mut self) -> FEIM_W<'_>

Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.

pub fn rtim(&mut self) -> RTIM_W<'_>

Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.

pub fn txim(&mut self) -> TXIM_W<'_>

Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.

pub fn rxim(&mut self) -> RXIM_W<'_>

Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.

pub fn dsrmim(&mut self) -> DSRMIM_W<'_>

Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.

pub fn dcdmim(&mut self) -> DCDMIM_W<'_>

Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.

pub fn ctsmim(&mut self) -> CTSMIM_W<'_>

Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.

pub fn rimim(&mut self) -> RIMIM_W<'_>

Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

impl W<u32, Reg<u32, _UARTICR>>

pub fn oeic(&mut self) -> OEIC_W<'_>

Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

pub fn beic(&mut self) -> BEIC_W<'_>

Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt.

pub fn peic(&mut self) -> PEIC_W<'_>

Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt.

pub fn feic(&mut self) -> FEIC_W<'_>

Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt.

pub fn rtic(&mut self) -> RTIC_W<'_>

Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

pub fn txic(&mut self) -> TXIC_W<'_>

Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt.

pub fn rxic(&mut self) -> RXIC_W<'_>

Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt.

pub fn dsrmic(&mut self) -> DSRMIC_W<'_>

Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

pub fn dcdmic(&mut self) -> DCDMIC_W<'_>

Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

pub fn ctsmic(&mut self) -> CTSMIC_W<'_>

Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

pub fn rimic(&mut self) -> RIMIC_W<'_>

Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

impl W<u32, Reg<u32, _UARTDMACR>>

pub fn dmaonerr(&mut self) -> DMAONERR_W<'_>

Bit 2 - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

pub fn txdmae(&mut self) -> TXDMAE_W<'_>

Bit 1 - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

pub fn rxdmae(&mut self) -> RXDMAE_W<'_>

Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

impl W<u32, Reg<u32, _SSPCR0>>

pub fn scr(&mut self) -> SCR_W<'_>

Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.

pub fn sph(&mut self) -> SPH_W<'_>

Bit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

pub fn spo(&mut self) -> SPO_W<'_>

Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

pub fn frf(&mut self) -> FRF_W<'_>

Bits 4:5 - Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.

pub fn dss(&mut self) -> DSS_W<'_>

Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.

impl W<u32, Reg<u32, _SSPCR1>>

pub fn sod(&mut self) -> SOD_W<'_>

Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.

pub fn ms(&mut self) -> MS_W<'_>

Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

pub fn sse(&mut self) -> SSE_W<'_>

Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

pub fn lbm(&mut self) -> LBM_W<'_>

Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

impl W<u32, Reg<u32, _SSPDR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.

impl W<u32, Reg<u32, _SSPCPSR>>

pub fn cpsdvsr(&mut self) -> CPSDVSR_W<'_>

Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.

impl W<u32, Reg<u32, _SSPIMSC>>

pub fn txim(&mut self) -> TXIM_W<'_>

Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.

pub fn rxim(&mut self) -> RXIM_W<'_>

Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.

pub fn rtim(&mut self) -> RTIM_W<'_>

Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

pub fn rorim(&mut self) -> RORIM_W<'_>

Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.

impl W<u32, Reg<u32, _SSPICR>>

pub fn rtic(&mut self) -> RTIC_W<'_>

Bit 1 - Clears the SSPRTINTR interrupt

pub fn roric(&mut self) -> RORIC_W<'_>

Bit 0 - Clears the SSPRORINTR interrupt

impl W<u32, Reg<u32, _SSPDMACR>>

pub fn txdmae(&mut self) -> TXDMAE_W<'_>

Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

pub fn rxdmae(&mut self) -> RXDMAE_W<'_>

Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

impl W<u32, Reg<u32, _IC_CON>>

pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W<'_>

Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n Reset value: 0x0.

pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W<'_>

Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0.

pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W<'_>

Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).

pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W<'_>

Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.

pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W<'_>

Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n Reset value: ENABLED

pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W<'_>

Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing

pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W<'_>

Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n 1: standard mode (100 kbit/s)\n\n 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n 3: high speed mode (3.4 Mbit/s)\n\n Note: This field is not applicable when IC_ULTRA_FAST_MODE=1

pub fn master_mode(&mut self) -> MASTER_MODE_W<'_>

Bit 0 - This bit controls whether the DW_apb_i2c master is enabled.\n\n NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.

impl W<u32, Reg<u32, _IC_TAR>>

pub fn special(&mut self) -> SPECIAL_W<'_>

Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0

pub fn gc_or_start(&mut self) -> GC_OR_START_W<'_>

Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0

pub fn ic_tar(&mut self) -> IC_TAR_W<'_>

Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.

impl W<u32, Reg<u32, _IC_SAR>>

pub fn ic_sar(&mut self) -> IC_SAR_W<'_>

Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values.

impl W<u32, Reg<u32, _IC_DATA_CMD>>

pub fn restart(&mut self) -> RESTART_W<'_>

Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received.\n\n 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n Reset value: 0x0

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received.\n\n - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0

pub fn cmd(&mut self) -> CMD_W<'_>

Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n Reset value: 0x0

pub fn dat(&mut self) -> DAT_W<'_>

Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n Reset value: 0x0

impl W<u32, Reg<u32, _IC_SS_SCL_HCNT>>

pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W<'_>

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.

impl W<u32, Reg<u32, _IC_SS_SCL_LCNT>>

pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W<'_>

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.

impl W<u32, Reg<u32, _IC_FS_SCL_HCNT>>

pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W<'_>

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.

impl W<u32, Reg<u32, _IC_FS_SCL_LCNT>>

pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W<'_>

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.

impl W<u32, Reg<u32, _IC_INTR_MASK>>

pub fn m_restart_det(&mut self) -> M_RESTART_DET_W<'_>

Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

pub fn m_gen_call(&mut self) -> M_GEN_CALL_W<'_>

Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_start_det(&mut self) -> M_START_DET_W<'_>

Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

pub fn m_stop_det(&mut self) -> M_STOP_DET_W<'_>

Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

pub fn m_activity(&mut self) -> M_ACTIVITY_W<'_>

Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

pub fn m_rx_done(&mut self) -> M_RX_DONE_W<'_>

Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W<'_>

Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_rd_req(&mut self) -> M_RD_REQ_W<'_>

Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W<'_>

Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_tx_over(&mut self) -> M_TX_OVER_W<'_>

Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_rx_full(&mut self) -> M_RX_FULL_W<'_>

Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_rx_over(&mut self) -> M_RX_OVER_W<'_>

Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

pub fn m_rx_under(&mut self) -> M_RX_UNDER_W<'_>

Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

impl W<u32, Reg<u32, _IC_RX_TL>>

pub fn rx_tl(&mut self) -> RX_TL_W<'_>

Bits 0:7 - Receive FIFO Threshold Level.\n\n Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.

impl W<u32, Reg<u32, _IC_TX_TL>>

pub fn tx_tl(&mut self) -> TX_TL_W<'_>

Bits 0:7 - Transmit FIFO Threshold Level.\n\n Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.

impl W<u32, Reg<u32, _IC_ENABLE>>

pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W<'_>

Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n Reset value: 0x0

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n Reset value: 0x0

impl W<u32, Reg<u32, _IC_SDA_HOLD>>

pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W<'_>

Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n Reset value: IC_DEFAULT_SDA_HOLD[23:16].

pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W<'_>

Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n Reset value: IC_DEFAULT_SDA_HOLD[15:0].

impl W<u32, Reg<u32, _IC_SLV_DATA_NACK_ONLY>>

pub fn nack(&mut self) -> NACK_W<'_>

Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0

impl W<u32, Reg<u32, _IC_DMA_CR>>

pub fn tdmae(&mut self) -> TDMAE_W<'_>

Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0

pub fn rdmae(&mut self) -> RDMAE_W<'_>

Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0

impl W<u32, Reg<u32, _IC_DMA_TDLR>>

pub fn dmatdl(&mut self) -> DMATDL_W<'_>

Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n Reset value: 0x0

impl W<u32, Reg<u32, _IC_DMA_RDLR>>

pub fn dmardl(&mut self) -> DMARDL_W<'_>

Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n Reset value: 0x0

impl W<u32, Reg<u32, _IC_SDA_SETUP>>

pub fn sda_setup(&mut self) -> SDA_SETUP_W<'_>

Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.

impl W<u32, Reg<u32, _IC_ACK_GENERAL_CALL>>

pub fn ack_gen_call(&mut self) -> ACK_GEN_CALL_W<'_>

Bit 0 - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).

impl W<u32, Reg<u32, _IC_FS_SPKLEN>>

pub fn ic_fs_spklen(&mut self) -> IC_FS_SPKLEN_W<'_>

Bits 0:7 - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.

impl W<u32, Reg<u32, _CS>>

pub fn rrobin(&mut self) -> RROBIN_W<'_>

Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n The first channel to be sampled will be the one currently indicated by AINSEL.\n AINSEL will be updated after each conversion with the newly-selected channel.

pub fn ainsel(&mut self) -> AINSEL_W<'_>

Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode.

pub fn err_sticky(&mut self) -> ERR_STICKY_W<'_>

Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear.

pub fn start_many(&mut self) -> START_MANY_W<'_>

Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.

pub fn start_once(&mut self) -> START_ONCE_W<'_>

Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted.

pub fn ts_en(&mut self) -> TS_EN_W<'_>

Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Power on ADC and enable its clock.\n 1 - enabled. 0 - disabled.

impl W<u32, Reg<u32, _FCS>>

pub fn thresh(&mut self) -> THRESH_W<'_>

Bits 24:27 - DREQ/IRQ asserted when level >= threshold

pub fn over(&mut self) -> OVER_W<'_>

Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear.

pub fn under(&mut self) -> UNDER_W<'_>

Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear.

pub fn dreq_en(&mut self) -> DREQ_EN_W<'_>

Bit 3 - If 1: assert DMA requests when FIFO contains data

pub fn err(&mut self) -> ERR_W<'_>

Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result

pub fn shift(&mut self) -> SHIFT_W<'_>

Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - If 1: write result to the FIFO after each conversion.

impl W<u32, Reg<u32, _DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 8:23 - Integer part of clock divisor.

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma.

impl W<u32, Reg<u32, _INTE>>

pub fn fifo(&mut self) -> FIFO_W<'_>

Bit 0 - Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field.

impl W<u32, Reg<u32, _INTF>>

pub fn fifo(&mut self) -> FIFO_W<'_>

Bit 0 - Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field.

impl W<u32, Reg<u32, _CH0_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH0_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH0_CTR>>

pub fn ch0_ctr(&mut self) -> CH0_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH0_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH0_TOP>>

pub fn ch0_top(&mut self) -> CH0_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH1_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH1_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH1_CTR>>

pub fn ch1_ctr(&mut self) -> CH1_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH1_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH1_TOP>>

pub fn ch1_top(&mut self) -> CH1_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH2_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH2_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH2_CTR>>

pub fn ch2_ctr(&mut self) -> CH2_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH2_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH2_TOP>>

pub fn ch2_top(&mut self) -> CH2_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH3_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH3_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH3_CTR>>

pub fn ch3_ctr(&mut self) -> CH3_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH3_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH3_TOP>>

pub fn ch3_top(&mut self) -> CH3_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH4_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH4_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH4_CTR>>

pub fn ch4_ctr(&mut self) -> CH4_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH4_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH4_TOP>>

pub fn ch4_top(&mut self) -> CH4_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH5_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH5_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH5_CTR>>

pub fn ch5_ctr(&mut self) -> CH5_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH5_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH5_TOP>>

pub fn ch5_top(&mut self) -> CH5_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH6_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH6_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH6_CTR>>

pub fn ch6_ctr(&mut self) -> CH6_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH6_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH6_TOP>>

pub fn ch6_top(&mut self) -> CH6_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH7_CSR>>

pub fn ph_adv(&mut self) -> PH_ADV_W<'_>

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

pub fn ph_ret(&mut self) -> PH_RET_W<'_>

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

pub fn divmode(&mut self) -> DIVMODE_W<'_>

Bits 4:5

pub fn b_inv(&mut self) -> B_INV_W<'_>

Bit 3 - Invert output B

pub fn a_inv(&mut self) -> A_INV_W<'_>

Bit 2 - Invert output A

pub fn ph_correct(&mut self) -> PH_CORRECT_W<'_>

Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable the PWM channel.

impl W<u32, Reg<u32, _CH7_DIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 4:11

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CH7_CTR>>

pub fn ch7_ctr(&mut self) -> CH7_CTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH7_CC>>

pub fn b(&mut self) -> B_W<'_>

Bits 16:31

pub fn a(&mut self) -> A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH7_TOP>>

pub fn ch7_top(&mut self) -> CH7_TOP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _EN>>

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTR>>

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTE>>

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTF>>

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0

impl W<u32, Reg<u32, _ARMED>>

pub fn armed(&mut self) -> ARMED_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _DBGPAUSE>>

pub fn dbg1(&mut self) -> DBG1_W<'_>

Bit 2 - Pause when processor 1 is in debug mode

pub fn dbg0(&mut self) -> DBG0_W<'_>

Bit 1 - Pause when processor 0 is in debug mode

impl W<u32, Reg<u32, _PAUSE>>

pub fn pause(&mut self) -> PAUSE_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTR>>

pub fn alarm_3(&mut self) -> ALARM_3_W<'_>

Bit 3

pub fn alarm_2(&mut self) -> ALARM_2_W<'_>

Bit 2

pub fn alarm_1(&mut self) -> ALARM_1_W<'_>

Bit 1

pub fn alarm_0(&mut self) -> ALARM_0_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTE>>

pub fn alarm_3(&mut self) -> ALARM_3_W<'_>

Bit 3

pub fn alarm_2(&mut self) -> ALARM_2_W<'_>

Bit 2

pub fn alarm_1(&mut self) -> ALARM_1_W<'_>

Bit 1

pub fn alarm_0(&mut self) -> ALARM_0_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTF>>

pub fn alarm_3(&mut self) -> ALARM_3_W<'_>

Bit 3

pub fn alarm_2(&mut self) -> ALARM_2_W<'_>

Bit 2

pub fn alarm_1(&mut self) -> ALARM_1_W<'_>

Bit 1

pub fn alarm_0(&mut self) -> ALARM_0_W<'_>

Bit 0

impl W<u32, Reg<u32, _CTRL>>

pub fn trigger(&mut self) -> TRIGGER_W<'_>

Bit 31 - Trigger a watchdog reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 30 - When not enabled the watchdog timer is paused

pub fn pause_dbg1(&mut self) -> PAUSE_DBG1_W<'_>

Bit 26 - Pause the watchdog timer when processor 1 is in debug mode

pub fn pause_dbg0(&mut self) -> PAUSE_DBG0_W<'_>

Bit 25 - Pause the watchdog timer when processor 0 is in debug mode

pub fn pause_jtag(&mut self) -> PAUSE_JTAG_W<'_>

Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric

impl W<u32, Reg<u32, _LOAD>>

pub fn load(&mut self) -> LOAD_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _TICK>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 9 - start / stop tick generation

pub fn cycles(&mut self) -> CYCLES_W<'_>

Bits 0:8 - Total number of clk_tick cycles before the next tick.

impl W<u32, Reg<u32, _CLKDIV_M1>>

pub fn clkdiv_m1(&mut self) -> CLKDIV_M1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SETUP_0>>

pub fn year(&mut self) -> YEAR_W<'_>

Bits 12:23 - Year

pub fn month(&mut self) -> MONTH_W<'_>

Bits 8:11 - Month (1..12)

pub fn day(&mut self) -> DAY_W<'_>

Bits 0:4 - Day of the month (1..31)

impl W<u32, Reg<u32, _SETUP_1>>

pub fn dotw(&mut self) -> DOTW_W<'_>

Bits 24:26 - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 16:20 - Hours

pub fn min(&mut self) -> MIN_W<'_>

Bits 8:13 - Minutes

pub fn sec(&mut self) -> SEC_W<'_>

Bits 0:5 - Seconds

impl W<u32, Reg<u32, _CTRL>>

pub fn force_notleapyear(&mut self) -> FORCE_NOTLEAPYEAR_W<'_>

Bit 8 - If set, leapyear is forced off.\n Useful for years divisible by 100 but not by 400

pub fn load(&mut self) -> LOAD_W<'_>

Bit 4 - Load RTC

pub fn rtc_enable(&mut self) -> RTC_ENABLE_W<'_>

Bit 0 - Enable RTC

impl W<u32, Reg<u32, _IRQ_SETUP_0>>

pub fn match_ena(&mut self) -> MATCH_ENA_W<'_>

Bit 28 - Global match enable. Don't change any other value while this one is enabled

pub fn year_ena(&mut self) -> YEAR_ENA_W<'_>

Bit 26 - Enable year matching

pub fn month_ena(&mut self) -> MONTH_ENA_W<'_>

Bit 25 - Enable month matching

pub fn day_ena(&mut self) -> DAY_ENA_W<'_>

Bit 24 - Enable day matching

pub fn year(&mut self) -> YEAR_W<'_>

Bits 12:23 - Year

pub fn month(&mut self) -> MONTH_W<'_>

Bits 8:11 - Month (1..12)

pub fn day(&mut self) -> DAY_W<'_>

Bits 0:4 - Day of the month (1..31)

impl W<u32, Reg<u32, _IRQ_SETUP_1>>

pub fn dotw_ena(&mut self) -> DOTW_ENA_W<'_>

Bit 31 - Enable day of the week matching

pub fn hour_ena(&mut self) -> HOUR_ENA_W<'_>

Bit 30 - Enable hour matching

pub fn min_ena(&mut self) -> MIN_ENA_W<'_>

Bit 29 - Enable minute matching

pub fn sec_ena(&mut self) -> SEC_ENA_W<'_>

Bit 28 - Enable second matching

pub fn dotw(&mut self) -> DOTW_W<'_>

Bits 24:26 - Day of the week

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 16:20 - Hours

pub fn min(&mut self) -> MIN_W<'_>

Bits 8:13 - Minutes

pub fn sec(&mut self) -> SEC_W<'_>

Bits 0:5 - Seconds

impl W<u32, Reg<u32, _INTE>>

pub fn rtc(&mut self) -> RTC_W<'_>

Bit 0

impl W<u32, Reg<u32, _INTF>>

pub fn rtc(&mut self) -> RTC_W<'_>

Bit 0

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 12:23 - On power-up this field is initialised to ENABLE\n The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.

pub fn freq_range(&mut self) -> FREQ_RANGE_W<'_>

Bits 0:11 - Controls the number of delay stages in the ROSC ring\n LOW uses stages 0 to 7\n MEDIUM uses stages 0 to 5\n HIGH uses stages 0 to 3\n TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n The clock output will not glitch when changing the range up one step at a time\n The clock output will glitch when changing the range down\n Note: the values here are gray coded which is why HIGH comes before TOOHIGH

impl W<u32, Reg<u32, _FREQA>>

pub fn passwd(&mut self) -> PASSWD_W<'_>

Bits 16:31 - Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0

pub fn ds3(&mut self) -> DS3_W<'_>

Bits 12:14 - Stage 3 drive strength

pub fn ds2(&mut self) -> DS2_W<'_>

Bits 8:10 - Stage 2 drive strength

pub fn ds1(&mut self) -> DS1_W<'_>

Bits 4:6 - Stage 1 drive strength

pub fn ds0(&mut self) -> DS0_W<'_>

Bits 0:2 - Stage 0 drive strength

impl W<u32, Reg<u32, _FREQB>>

pub fn passwd(&mut self) -> PASSWD_W<'_>

Bits 16:31 - Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0

pub fn ds7(&mut self) -> DS7_W<'_>

Bits 12:14 - Stage 7 drive strength

pub fn ds6(&mut self) -> DS6_W<'_>

Bits 8:10 - Stage 6 drive strength

pub fn ds5(&mut self) -> DS5_W<'_>

Bits 4:6 - Stage 5 drive strength

pub fn ds4(&mut self) -> DS4_W<'_>

Bits 0:2 - Stage 4 drive strength

impl W<u32, Reg<u32, _DIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 0:11 - set to 0xaa0 + div where\n div = 0 divides by 32\n div = 1-31 divides by div\n any other value sets div=0 and therefore divides by 32\n this register resets to div=16

impl W<u32, Reg<u32, _PHASE>>

pub fn passwd(&mut self) -> PASSWD_W<'_>

Bits 4:11 - set to 0xaa0\n any other value enables the output with shift=0

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 3 - enable the phase-shifted output\n this can be changed on-the-fly

pub fn flip(&mut self) -> FLIP_W<'_>

Bit 2 - invert the phase-shifted output\n this is ignored when div=1

pub fn shift(&mut self) -> SHIFT_W<'_>

Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks\n this can be changed on-the-fly\n must be set to 0 before setting div=1

impl W<u32, Reg<u32, _STATUS>>

pub fn badwrite(&mut self) -> BADWRITE_W<'_>

Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _VREG>>

pub fn vsel(&mut self) -> VSEL_W<'_>

Bits 4:7 - output voltage select\n 0000 to 0101 - 0.80V\n 0110 - 0.85V\n 0111 - 0.90V\n 1000 - 0.95V\n 1001 - 1.00V\n 1010 - 1.05V\n 1011 - 1.10V (default)\n 1100 - 1.15V\n 1101 - 1.20V\n 1110 - 1.25V\n 1111 - 1.30V

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - high impedance mode select\n 0=not in high impedance mode, 1=in high impedance mode

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - enable\n 0=not enabled, 1=enabled

impl W<u32, Reg<u32, _BOD>>

pub fn vsel(&mut self) -> VSEL_W<'_>

Bits 4:7 - threshold select\n 0000 - 0.473V\n 0001 - 0.516V\n 0010 - 0.559V\n 0011 - 0.602V\n 0100 - 0.645V\n 0101 - 0.688V\n 0110 - 0.731V\n 0111 - 0.774V\n 1000 - 0.817V\n 1001 - 0.860V (default)\n 1010 - 0.903V\n 1011 - 0.946V\n 1100 - 0.989V\n 1101 - 1.032V\n 1110 - 1.075V\n 1111 - 1.118V

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - enable\n 0=not enabled, 1=enabled

impl W<u32, Reg<u32, _CHIP_RESET>>

pub fn psm_restart_flag(&mut self) -> PSM_RESTART_FLAG_W<'_>

Bit 24 - This is set by psm_restart from the debugger.\n Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.

impl W<u32, Reg<u32, _CH0_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (0).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH1_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (1).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH2_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (2).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH3_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (3).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH4_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (4).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH5_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (5).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH6_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (6).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH7_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (7).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH8_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (8).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH9_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (9).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH10_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (10).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _CH11_CTRL_TRIG>>

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (11).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

impl W<u32, Reg<u32, _INTE0>>

pub fn inte0(&mut self) -> INTE0_W<'_>

Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0.

impl W<u32, Reg<u32, _INTF0>>

pub fn intf0(&mut self) -> INTF0_W<'_>

Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

impl W<u32, Reg<u32, _INTS0>>

pub fn ints0(&mut self) -> INTS0_W<'_>

Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here.

impl W<u32, Reg<u32, _INTE1>>

pub fn inte1(&mut self) -> INTE1_W<'_>

Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1.

impl W<u32, Reg<u32, _INTF1>>

pub fn intf1(&mut self) -> INTF1_W<'_>

Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

impl W<u32, Reg<u32, _INTS1>>

pub fn ints1(&mut self) -> INTS1_W<'_>

Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here.

impl W<u32, Reg<u32, _TIMER0>>

pub fn x(&mut self) -> X_W<'_>

Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

pub fn y(&mut self) -> Y_W<'_>

Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

impl W<u32, Reg<u32, _TIMER1>>

pub fn x(&mut self) -> X_W<'_>

Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

pub fn y(&mut self) -> Y_W<'_>

Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

impl W<u32, Reg<u32, _MULTI_CHAN_TRIGGER>>

pub fn multi_chan_trigger(&mut self) -> MULTI_CHAN_TRIGGER_W<'_>

Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.

impl W<u32, Reg<u32, _SNIFF_CTRL>>

pub fn out_inv(&mut self) -> OUT_INV_W<'_>

Bit 11 - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

pub fn out_rev(&mut self) -> OUT_REV_W<'_>

Bit 10 - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.

pub fn calc(&mut self) -> CALC_W<'_>

Bits 5:8

pub fn dmach(&mut self) -> DMACH_W<'_>

Bits 1:4 - DMA channel for Sniffer to observe

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable sniffer

impl W<u32, Reg<u32, _CHAN_ABORT>>

pub fn chan_abort(&mut self) -> CHAN_ABORT_W<'_>

Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.

impl W<u32, Reg<u32, _ADDR_ENDP>>

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Device endpoint to send data to. Only valid for HOST mode.

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.

impl W<u32, Reg<u32, _ADDR_ENDP1>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP2>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP3>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP4>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP5>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP6>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP7>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP8>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP9>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP10>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP11>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP12>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP13>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP14>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _ADDR_ENDP15>>

pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<'_>

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

pub fn intep_dir(&mut self) -> INTEP_DIR_W<'_>

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

pub fn endpoint(&mut self) -> ENDPOINT_W<'_>

Bits 16:19 - Endpoint number of the interrupt endpoint

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Device address

impl W<u32, Reg<u32, _MAIN_CTRL>>

pub fn sim_timing(&mut self) -> SIM_TIMING_W<'_>

Bit 31 - Reduced timings for simulation

pub fn host_ndevice(&mut self) -> HOST_NDEVICE_W<'_>

Bit 1 - Device mode = 0, Host mode = 1

pub fn controller_en(&mut self) -> CONTROLLER_EN_W<'_>

Bit 0 - Enable controller

impl W<u32, Reg<u32, _SOF_WR>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _SIE_CTRL>>

pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W<'_>

Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL

pub fn ep0_double_buf(&mut self) -> EP0_DOUBLE_BUF_W<'_>

Bit 30 - Device: EP0 single buffered = 0, double buffered = 1

pub fn ep0_int_1buf(&mut self) -> EP0_INT_1BUF_W<'_>

Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0

pub fn ep0_int_2buf(&mut self) -> EP0_INT_2BUF_W<'_>

Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0

pub fn ep0_int_nak(&mut self) -> EP0_INT_NAK_W<'_>

Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK

pub fn direct_en(&mut self) -> DIRECT_EN_W<'_>

Bit 26 - Direct bus drive enable

pub fn direct_dp(&mut self) -> DIRECT_DP_W<'_>

Bit 25 - Direct control of DP

pub fn direct_dm(&mut self) -> DIRECT_DM_W<'_>

Bit 24 - Direct control of DM

pub fn transceiver_pd(&mut self) -> TRANSCEIVER_PD_W<'_>

Bit 18 - Power down bus transceiver

pub fn rpu_opt(&mut self) -> RPU_OPT_W<'_>

Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)

pub fn pullup_en(&mut self) -> PULLUP_EN_W<'_>

Bit 16 - Device: Enable pull up resistor

pub fn pulldown_en(&mut self) -> PULLDOWN_EN_W<'_>

Bit 15 - Host: Enable pull down resistors

pub fn reset_bus(&mut self) -> RESET_BUS_W<'_>

Bit 13 - Host: Reset bus

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend.

pub fn vbus_en(&mut self) -> VBUS_EN_W<'_>

Bit 11 - Host: Enable VBUS

pub fn keep_alive_en(&mut self) -> KEEP_ALIVE_EN_W<'_>

Bit 10 - Host: Enable keep alive packet (for low speed bus)

pub fn sof_en(&mut self) -> SOF_EN_W<'_>

Bit 9 - Host: Enable SOF generation (for full speed bus)

pub fn sof_sync(&mut self) -> SOF_SYNC_W<'_>

Bit 8 - Host: Delay packet(s) until after SOF

pub fn preamble_en(&mut self) -> PREAMBLE_EN_W<'_>

Bit 6 - Host: Preable enable for LS device on FS hub

pub fn stop_trans(&mut self) -> STOP_TRANS_W<'_>

Bit 4 - Host: Stop transaction

pub fn receive_data(&mut self) -> RECEIVE_DATA_W<'_>

Bit 3 - Host: Receive transaction (IN to host)

pub fn send_data(&mut self) -> SEND_DATA_W<'_>

Bit 2 - Host: Send transaction (OUT from host)

pub fn send_setup(&mut self) -> SEND_SETUP_W<'_>

Bit 1 - Host: Send Setup packet

pub fn start_trans(&mut self) -> START_TRANS_W<'_>

Bit 0 - Host: Start transaction

impl W<u32, Reg<u32, _SIE_STATUS>>

pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W<'_>

Bit 31 - Data Sequence Error.\n\n The device can raise a sequence error in the following conditions:\n\n * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n The host can raise a data sequence error in the following conditions:\n\n * An IN packet from the device has the wrong data PID

pub fn ack_rec(&mut self) -> ACK_REC_W<'_>

Bit 30 - ACK received. Raised by both host and device.

pub fn stall_rec(&mut self) -> STALL_REC_W<'_>

Bit 29 - Host: STALL received

pub fn nak_rec(&mut self) -> NAK_REC_W<'_>

Bit 28 - Host: NAK received

pub fn rx_timeout(&mut self) -> RX_TIMEOUT_W<'_>

Bit 27 - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.

pub fn rx_overflow(&mut self) -> RX_OVERFLOW_W<'_>

Bit 26 - RX overflow is raised by the Serial RX engine if the incoming data is too fast.

pub fn bit_stuff_error(&mut self) -> BIT_STUFF_ERROR_W<'_>

Bit 25 - Bit Stuff Error. Raised by the Serial RX engine.

pub fn crc_error(&mut self) -> CRC_ERROR_W<'_>

Bit 24 - CRC Error. Raised by the Serial RX engine.

pub fn bus_reset(&mut self) -> BUS_RESET_W<'_>

Bit 19 - Device: bus reset received

pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<'_>

Bit 18 - Transaction complete.\n\n Raised by device if:\n\n * An IN or OUT packet is sent with the LAST_BUFF bit set in the buffer control register\n\n Raised by host if:\n\n * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the LAST_BUFF bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the LAST_BUFF bit is set

pub fn setup_rec(&mut self) -> SETUP_REC_W<'_>

Bit 17 - Device: Setup packet received

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume.

impl W<u32, Reg<u32, _INT_EP_CTRL>>

pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W<'_>

Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15

impl W<u32, Reg<u32, _EP_ABORT>>

pub fn ep15_out(&mut self) -> EP15_OUT_W<'_>

Bit 31

pub fn ep15_in(&mut self) -> EP15_IN_W<'_>

Bit 30

pub fn ep14_out(&mut self) -> EP14_OUT_W<'_>

Bit 29

pub fn ep14_in(&mut self) -> EP14_IN_W<'_>

Bit 28

pub fn ep13_out(&mut self) -> EP13_OUT_W<'_>

Bit 27

pub fn ep13_in(&mut self) -> EP13_IN_W<'_>

Bit 26

pub fn ep12_out(&mut self) -> EP12_OUT_W<'_>

Bit 25

pub fn ep12_in(&mut self) -> EP12_IN_W<'_>

Bit 24

pub fn ep11_out(&mut self) -> EP11_OUT_W<'_>

Bit 23

pub fn ep11_in(&mut self) -> EP11_IN_W<'_>

Bit 22

pub fn ep10_out(&mut self) -> EP10_OUT_W<'_>

Bit 21

pub fn ep10_in(&mut self) -> EP10_IN_W<'_>

Bit 20

pub fn ep9_out(&mut self) -> EP9_OUT_W<'_>

Bit 19

pub fn ep9_in(&mut self) -> EP9_IN_W<'_>

Bit 18

pub fn ep8_out(&mut self) -> EP8_OUT_W<'_>

Bit 17

pub fn ep8_in(&mut self) -> EP8_IN_W<'_>

Bit 16

pub fn ep7_out(&mut self) -> EP7_OUT_W<'_>

Bit 15

pub fn ep7_in(&mut self) -> EP7_IN_W<'_>

Bit 14

pub fn ep6_out(&mut self) -> EP6_OUT_W<'_>

Bit 13

pub fn ep6_in(&mut self) -> EP6_IN_W<'_>

Bit 12

pub fn ep5_out(&mut self) -> EP5_OUT_W<'_>

Bit 11

pub fn ep5_in(&mut self) -> EP5_IN_W<'_>

Bit 10

pub fn ep4_out(&mut self) -> EP4_OUT_W<'_>

Bit 9

pub fn ep4_in(&mut self) -> EP4_IN_W<'_>

Bit 8

pub fn ep3_out(&mut self) -> EP3_OUT_W<'_>

Bit 7

pub fn ep3_in(&mut self) -> EP3_IN_W<'_>

Bit 6

pub fn ep2_out(&mut self) -> EP2_OUT_W<'_>

Bit 5

pub fn ep2_in(&mut self) -> EP2_IN_W<'_>

Bit 4

pub fn ep1_out(&mut self) -> EP1_OUT_W<'_>

Bit 3

pub fn ep1_in(&mut self) -> EP1_IN_W<'_>

Bit 2

pub fn ep0_out(&mut self) -> EP0_OUT_W<'_>

Bit 1

pub fn ep0_in(&mut self) -> EP0_IN_W<'_>

Bit 0

impl W<u32, Reg<u32, _EP_ABORT_DONE>>

pub fn ep15_out(&mut self) -> EP15_OUT_W<'_>

Bit 31

pub fn ep15_in(&mut self) -> EP15_IN_W<'_>

Bit 30

pub fn ep14_out(&mut self) -> EP14_OUT_W<'_>

Bit 29

pub fn ep14_in(&mut self) -> EP14_IN_W<'_>

Bit 28

pub fn ep13_out(&mut self) -> EP13_OUT_W<'_>

Bit 27

pub fn ep13_in(&mut self) -> EP13_IN_W<'_>

Bit 26

pub fn ep12_out(&mut self) -> EP12_OUT_W<'_>

Bit 25

pub fn ep12_in(&mut self) -> EP12_IN_W<'_>

Bit 24

pub fn ep11_out(&mut self) -> EP11_OUT_W<'_>

Bit 23

pub fn ep11_in(&mut self) -> EP11_IN_W<'_>

Bit 22

pub fn ep10_out(&mut self) -> EP10_OUT_W<'_>

Bit 21

pub fn ep10_in(&mut self) -> EP10_IN_W<'_>

Bit 20

pub fn ep9_out(&mut self) -> EP9_OUT_W<'_>

Bit 19

pub fn ep9_in(&mut self) -> EP9_IN_W<'_>

Bit 18

pub fn ep8_out(&mut self) -> EP8_OUT_W<'_>

Bit 17

pub fn ep8_in(&mut self) -> EP8_IN_W<'_>

Bit 16

pub fn ep7_out(&mut self) -> EP7_OUT_W<'_>

Bit 15

pub fn ep7_in(&mut self) -> EP7_IN_W<'_>

Bit 14

pub fn ep6_out(&mut self) -> EP6_OUT_W<'_>

Bit 13

pub fn ep6_in(&mut self) -> EP6_IN_W<'_>

Bit 12

pub fn ep5_out(&mut self) -> EP5_OUT_W<'_>

Bit 11

pub fn ep5_in(&mut self) -> EP5_IN_W<'_>

Bit 10

pub fn ep4_out(&mut self) -> EP4_OUT_W<'_>

Bit 9

pub fn ep4_in(&mut self) -> EP4_IN_W<'_>

Bit 8

pub fn ep3_out(&mut self) -> EP3_OUT_W<'_>

Bit 7

pub fn ep3_in(&mut self) -> EP3_IN_W<'_>

Bit 6

pub fn ep2_out(&mut self) -> EP2_OUT_W<'_>

Bit 5

pub fn ep2_in(&mut self) -> EP2_IN_W<'_>

Bit 4

pub fn ep1_out(&mut self) -> EP1_OUT_W<'_>

Bit 3

pub fn ep1_in(&mut self) -> EP1_IN_W<'_>

Bit 2

pub fn ep0_out(&mut self) -> EP0_OUT_W<'_>

Bit 1

pub fn ep0_in(&mut self) -> EP0_IN_W<'_>

Bit 0

impl W<u32, Reg<u32, _EP_STALL_ARM>>

pub fn ep0_out(&mut self) -> EP0_OUT_W<'_>

Bit 1

pub fn ep0_in(&mut self) -> EP0_IN_W<'_>

Bit 0

impl W<u32, Reg<u32, _NAK_POLL>>

pub fn delay_fs(&mut self) -> DELAY_FS_W<'_>

Bits 16:25 - NAK polling interval for a full speed device

pub fn delay_ls(&mut self) -> DELAY_LS_W<'_>

Bits 0:9 - NAK polling interval for a low speed device

impl W<u32, Reg<u32, _EP_STATUS_STALL_NAK>>

pub fn ep15_out(&mut self) -> EP15_OUT_W<'_>

Bit 31

pub fn ep15_in(&mut self) -> EP15_IN_W<'_>

Bit 30

pub fn ep14_out(&mut self) -> EP14_OUT_W<'_>

Bit 29

pub fn ep14_in(&mut self) -> EP14_IN_W<'_>

Bit 28

pub fn ep13_out(&mut self) -> EP13_OUT_W<'_>

Bit 27

pub fn ep13_in(&mut self) -> EP13_IN_W<'_>

Bit 26

pub fn ep12_out(&mut self) -> EP12_OUT_W<'_>

Bit 25

pub fn ep12_in(&mut self) -> EP12_IN_W<'_>

Bit 24

pub fn ep11_out(&mut self) -> EP11_OUT_W<'_>

Bit 23

pub fn ep11_in(&mut self) -> EP11_IN_W<'_>

Bit 22

pub fn ep10_out(&mut self) -> EP10_OUT_W<'_>

Bit 21

pub fn ep10_in(&mut self) -> EP10_IN_W<'_>

Bit 20

pub fn ep9_out(&mut self) -> EP9_OUT_W<'_>

Bit 19

pub fn ep9_in(&mut self) -> EP9_IN_W<'_>

Bit 18

pub fn ep8_out(&mut self) -> EP8_OUT_W<'_>

Bit 17

pub fn ep8_in(&mut self) -> EP8_IN_W<'_>

Bit 16

pub fn ep7_out(&mut self) -> EP7_OUT_W<'_>

Bit 15

pub fn ep7_in(&mut self) -> EP7_IN_W<'_>

Bit 14

pub fn ep6_out(&mut self) -> EP6_OUT_W<'_>

Bit 13

pub fn ep6_in(&mut self) -> EP6_IN_W<'_>

Bit 12

pub fn ep5_out(&mut self) -> EP5_OUT_W<'_>

Bit 11

pub fn ep5_in(&mut self) -> EP5_IN_W<'_>

Bit 10

pub fn ep4_out(&mut self) -> EP4_OUT_W<'_>

Bit 9

pub fn ep4_in(&mut self) -> EP4_IN_W<'_>

Bit 8

pub fn ep3_out(&mut self) -> EP3_OUT_W<'_>

Bit 7

pub fn ep3_in(&mut self) -> EP3_IN_W<'_>

Bit 6

pub fn ep2_out(&mut self) -> EP2_OUT_W<'_>

Bit 5

pub fn ep2_in(&mut self) -> EP2_IN_W<'_>

Bit 4

pub fn ep1_out(&mut self) -> EP1_OUT_W<'_>

Bit 3

pub fn ep1_in(&mut self) -> EP1_IN_W<'_>

Bit 2

pub fn ep0_out(&mut self) -> EP0_OUT_W<'_>

Bit 1

pub fn ep0_in(&mut self) -> EP0_IN_W<'_>

Bit 0

impl W<u32, Reg<u32, _USB_MUXING>>

pub fn softcon(&mut self) -> SOFTCON_W<'_>

Bit 3

pub fn to_digital_pad(&mut self) -> TO_DIGITAL_PAD_W<'_>

Bit 2

pub fn to_extphy(&mut self) -> TO_EXTPHY_W<'_>

Bit 1

pub fn to_phy(&mut self) -> TO_PHY_W<'_>

Bit 0

impl W<u32, Reg<u32, _USB_PWR>>

pub fn overcurr_detect_en(&mut self) -> OVERCURR_DETECT_EN_W<'_>

Bit 5

pub fn overcurr_detect(&mut self) -> OVERCURR_DETECT_W<'_>

Bit 4

pub fn vbus_detect_override_en(&mut self) -> VBUS_DETECT_OVERRIDE_EN_W<'_>

Bit 3

pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<'_>

Bit 2

pub fn vbus_en_override_en(&mut self) -> VBUS_EN_OVERRIDE_EN_W<'_>

Bit 1

pub fn vbus_en(&mut self) -> VBUS_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _USBPHY_DIRECT>>

pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W<'_>

Bit 15 - TX_DIFFMODE=0: Single ended mode\n TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)

pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W<'_>

Bit 14 - TX_FSSLEW=0: Low speed slew rate\n TX_FSSLEW=1: Full speed slew rate

pub fn tx_pd(&mut self) -> TX_PD_W<'_>

Bit 13 - TX power down override (if override enable is set). 1 = powered down.

pub fn rx_pd(&mut self) -> RX_PD_W<'_>

Bit 12 - RX power down override (if override enable is set). 1 = powered down.

pub fn tx_dm(&mut self) -> TX_DM_W<'_>

Bit 11 - Output data. TX_DIFFMODE=1, Ignored\n TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM

pub fn tx_dp(&mut self) -> TX_DP_W<'_>

Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP

pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W<'_>

Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored.\n If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving

pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W<'_>

Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving

pub fn dm_pulldn_en(&mut self) -> DM_PULLDN_EN_W<'_>

Bit 6 - DM pull down enable

pub fn dm_pullup_en(&mut self) -> DM_PULLUP_EN_W<'_>

Bit 5 - DM pull up enable

pub fn dm_pullup_hisel(&mut self) -> DM_PULLUP_HISEL_W<'_>

Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2

pub fn dp_pulldn_en(&mut self) -> DP_PULLDN_EN_W<'_>

Bit 2 - DP pull down enable

pub fn dp_pullup_en(&mut self) -> DP_PULLUP_EN_W<'_>

Bit 1 - DP pull up enable

pub fn dp_pullup_hisel(&mut self) -> DP_PULLUP_HISEL_W<'_>

Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2

impl W<u32, Reg<u32, _USBPHY_DIRECT_OVERRIDE>>

pub fn tx_diffmode_override_en(&mut self) -> TX_DIFFMODE_OVERRIDE_EN_W<'_>

Bit 15

pub fn dm_pullup_override_en(&mut self) -> DM_PULLUP_OVERRIDE_EN_W<'_>

Bit 12

pub fn tx_fsslew_override_en(&mut self) -> TX_FSSLEW_OVERRIDE_EN_W<'_>

Bit 11

pub fn tx_pd_override_en(&mut self) -> TX_PD_OVERRIDE_EN_W<'_>

Bit 10

pub fn rx_pd_override_en(&mut self) -> RX_PD_OVERRIDE_EN_W<'_>

Bit 9

pub fn tx_dm_override_en(&mut self) -> TX_DM_OVERRIDE_EN_W<'_>

Bit 8

pub fn tx_dp_override_en(&mut self) -> TX_DP_OVERRIDE_EN_W<'_>

Bit 7

pub fn tx_dm_oe_override_en(&mut self) -> TX_DM_OE_OVERRIDE_EN_W<'_>

Bit 6

pub fn tx_dp_oe_override_en(&mut self) -> TX_DP_OE_OVERRIDE_EN_W<'_>

Bit 5

pub fn dm_pulldn_en_override_en(&mut self) -> DM_PULLDN_EN_OVERRIDE_EN_W<'_>

Bit 4

pub fn dp_pulldn_en_override_en(&mut self) -> DP_PULLDN_EN_OVERRIDE_EN_W<'_>

Bit 3

pub fn dp_pullup_en_override_en(&mut self) -> DP_PULLUP_EN_OVERRIDE_EN_W<'_>

Bit 2

pub fn dm_pullup_hisel_override_en(
    &mut self
) -> DM_PULLUP_HISEL_OVERRIDE_EN_W<'_>

Bit 1

pub fn dp_pullup_hisel_override_en(
    &mut self
) -> DP_PULLUP_HISEL_OVERRIDE_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _USBPHY_TRIM>>

pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W<'_>

Bits 8:12 - Value to drive to USB PHY\n DM pulldown resistor trim control\n Experimental data suggests that the reset value will work, but this register allows adjustment if required

pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W<'_>

Bits 0:4 - Value to drive to USB PHY\n DP pulldown resistor trim control\n Experimental data suggests that the reset value will work, but this register allows adjustment if required

impl W<u32, Reg<u32, _INTE>>

pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W<'_>

Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.

pub fn abort_done(&mut self) -> ABORT_DONE_W<'_>

Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.

pub fn dev_sof(&mut self) -> DEV_SOF_W<'_>

Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD

pub fn setup_req(&mut self) -> SETUP_REQ_W<'_>

Bit 16 - Device. Source: SIE_STATUS.SETUP_REC

pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W<'_>

Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME

pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W<'_>

Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED

pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W<'_>

Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED

pub fn bus_reset(&mut self) -> BUS_RESET_W<'_>

Bit 12 - Source: SIE_STATUS.BUS_RESET

pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<'_>

Bit 11 - Source: SIE_STATUS.VBUS_DETECT

pub fn stall(&mut self) -> STALL_W<'_>

Bit 10 - Source: SIE_STATUS.STALL_REC

pub fn error_crc(&mut self) -> ERROR_CRC_W<'_>

Bit 9 - Source: SIE_STATUS.CRC_ERROR

pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W<'_>

Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR

pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W<'_>

Bit 7 - Source: SIE_STATUS.RX_OVERFLOW

pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W<'_>

Bit 6 - Source: SIE_STATUS.RX_TIMEOUT

pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W<'_>

Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR

pub fn buff_status(&mut self) -> BUFF_STATUS_W<'_>

Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.

pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<'_>

Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.

pub fn host_sof(&mut self) -> HOST_SOF_W<'_>

Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD

pub fn host_resume(&mut self) -> HOST_RESUME_W<'_>

Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME

pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W<'_>

Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED

impl W<u32, Reg<u32, _INTF>>

pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W<'_>

Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.

pub fn abort_done(&mut self) -> ABORT_DONE_W<'_>

Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.

pub fn dev_sof(&mut self) -> DEV_SOF_W<'_>

Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD

pub fn setup_req(&mut self) -> SETUP_REQ_W<'_>

Bit 16 - Device. Source: SIE_STATUS.SETUP_REC

pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W<'_>

Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME

pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W<'_>

Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED

pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W<'_>

Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED

pub fn bus_reset(&mut self) -> BUS_RESET_W<'_>

Bit 12 - Source: SIE_STATUS.BUS_RESET

pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<'_>

Bit 11 - Source: SIE_STATUS.VBUS_DETECT

pub fn stall(&mut self) -> STALL_W<'_>

Bit 10 - Source: SIE_STATUS.STALL_REC

pub fn error_crc(&mut self) -> ERROR_CRC_W<'_>

Bit 9 - Source: SIE_STATUS.CRC_ERROR

pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W<'_>

Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR

pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W<'_>

Bit 7 - Source: SIE_STATUS.RX_OVERFLOW

pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W<'_>

Bit 6 - Source: SIE_STATUS.RX_TIMEOUT

pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W<'_>

Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR

pub fn buff_status(&mut self) -> BUFF_STATUS_W<'_>

Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.

pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<'_>

Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.

pub fn host_sof(&mut self) -> HOST_SOF_W<'_>

Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD

pub fn host_resume(&mut self) -> HOST_RESUME_W<'_>

Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME

pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W<'_>

Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED

impl W<u32, Reg<u32, _CTRL>>

pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W<'_>

Bits 8:11 - Force clock dividers to restart their count and clear fractional\n accumulators. Restart multiple dividers to synchronise them.

pub fn sm_restart(&mut self) -> SM_RESTART_W<'_>

Bits 4:7 - Clear internal SM state which is otherwise difficult to access\n (e.g. shift counters). Self-clearing.

pub fn sm_enable(&mut self) -> SM_ENABLE_W<'_>

Bits 0:3 - Enable state machine

impl W<u32, Reg<u32, _FDEBUG>>

pub fn txstall(&mut self) -> TXSTALL_W<'_>

Bits 24:27 - State machine has stalled on empty TX FIFO. Write 1 to clear.

pub fn txover(&mut self) -> TXOVER_W<'_>

Bits 16:19 - TX FIFO overflow has occurred. Write 1 to clear.

pub fn rxunder(&mut self) -> RXUNDER_W<'_>

Bits 8:11 - RX FIFO underflow has occurred. Write 1 to clear.

pub fn rxstall(&mut self) -> RXSTALL_W<'_>

Bits 0:3 - State machine has stalled on full RX FIFO. Write 1 to clear.

impl W<u32, Reg<u32, _IRQ>>

pub fn irq(&mut self) -> IRQ_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _IRQ_FORCE>>

pub fn irq_force(&mut self) -> IRQ_FORCE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _INSTR_MEM0>>

pub fn instr_mem0(&mut self) -> INSTR_MEM0_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM1>>

pub fn instr_mem1(&mut self) -> INSTR_MEM1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM2>>

pub fn instr_mem2(&mut self) -> INSTR_MEM2_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM3>>

pub fn instr_mem3(&mut self) -> INSTR_MEM3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM4>>

pub fn instr_mem4(&mut self) -> INSTR_MEM4_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM5>>

pub fn instr_mem5(&mut self) -> INSTR_MEM5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM6>>

pub fn instr_mem6(&mut self) -> INSTR_MEM6_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM7>>

pub fn instr_mem7(&mut self) -> INSTR_MEM7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM8>>

pub fn instr_mem8(&mut self) -> INSTR_MEM8_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM9>>

pub fn instr_mem9(&mut self) -> INSTR_MEM9_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM10>>

pub fn instr_mem10(&mut self) -> INSTR_MEM10_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM11>>

pub fn instr_mem11(&mut self) -> INSTR_MEM11_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM12>>

pub fn instr_mem12(&mut self) -> INSTR_MEM12_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM13>>

pub fn instr_mem13(&mut self) -> INSTR_MEM13_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM14>>

pub fn instr_mem14(&mut self) -> INSTR_MEM14_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM15>>

pub fn instr_mem15(&mut self) -> INSTR_MEM15_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM16>>

pub fn instr_mem16(&mut self) -> INSTR_MEM16_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM17>>

pub fn instr_mem17(&mut self) -> INSTR_MEM17_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM18>>

pub fn instr_mem18(&mut self) -> INSTR_MEM18_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM19>>

pub fn instr_mem19(&mut self) -> INSTR_MEM19_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM20>>

pub fn instr_mem20(&mut self) -> INSTR_MEM20_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM21>>

pub fn instr_mem21(&mut self) -> INSTR_MEM21_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM22>>

pub fn instr_mem22(&mut self) -> INSTR_MEM22_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM23>>

pub fn instr_mem23(&mut self) -> INSTR_MEM23_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM24>>

pub fn instr_mem24(&mut self) -> INSTR_MEM24_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM25>>

pub fn instr_mem25(&mut self) -> INSTR_MEM25_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM26>>

pub fn instr_mem26(&mut self) -> INSTR_MEM26_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM27>>

pub fn instr_mem27(&mut self) -> INSTR_MEM27_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM28>>

pub fn instr_mem28(&mut self) -> INSTR_MEM28_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM29>>

pub fn instr_mem29(&mut self) -> INSTR_MEM29_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM30>>

pub fn instr_mem30(&mut self) -> INSTR_MEM30_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INSTR_MEM31>>

pub fn instr_mem31(&mut self) -> INSTR_MEM31_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SM0_CLKDIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 8:15 - Fractional part of clock divider

impl W<u32, Reg<u32, _SM0_EXECCTRL>>

pub fn side_en(&mut self) -> SIDE_EN_W<'_>

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<'_>

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

pub fn jmp_pin(&mut self) -> JMP_PIN_W<'_>

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<'_>

Bits 19:23 - Which data bit to use for inline OUT enable

pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<'_>

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

pub fn out_sticky(&mut self) -> OUT_STICKY_W<'_>

Bit 17 - Continuously assert the most recent OUT/SET to the pins

pub fn wrap_top(&mut self) -> WRAP_TOP_W<'_>

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<'_>

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

pub fn status_sel(&mut self) -> STATUS_SEL_W<'_>

Bit 4 - Comparison used for the MOV x, STATUS instruction.

pub fn status_n(&mut self) -> STATUS_N_W<'_>

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

impl W<u32, Reg<u32, _SM0_SHIFTCTRL>>

pub fn fjoin_rx(&mut self) -> FJOIN_RX_W<'_>

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn fjoin_tx(&mut self) -> FJOIN_TX_W<'_>

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn pull_thresh(&mut self) -> PULL_THRESH_W<'_>

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

pub fn push_thresh(&mut self) -> PUSH_THRESH_W<'_>

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W<'_>

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W<'_>

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

pub fn autopull(&mut self) -> AUTOPULL_W<'_>

Bit 17 - Pull automatically when the output shift register is emptied

pub fn autopush(&mut self) -> AUTOPUSH_W<'_>

Bit 16 - Push automatically when the input shift register is filled

impl W<u32, Reg<u32, _SM0_INSTR>>

pub fn sm0_instr(&mut self) -> SM0_INSTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SM0_PINCTRL>>

pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<'_>

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

pub fn set_count(&mut self) -> SET_COUNT_W<'_>

Bits 26:28 - The number of pins asserted by a SET. Max of 5

pub fn out_count(&mut self) -> OUT_COUNT_W<'_>

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

pub fn in_base(&mut self) -> IN_BASE_W<'_>

Bits 15:19 - The virtual pin corresponding to IN bit 0

pub fn sideset_base(&mut self) -> SIDESET_BASE_W<'_>

Bits 10:14 - The virtual pin corresponding to delay field bit 0

pub fn set_base(&mut self) -> SET_BASE_W<'_>

Bits 5:9 - The virtual pin corresponding to SET bit 0

pub fn out_base(&mut self) -> OUT_BASE_W<'_>

Bits 0:4 - The virtual pin corresponding to OUT bit 0

impl W<u32, Reg<u32, _SM1_CLKDIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 8:15 - Fractional part of clock divider

impl W<u32, Reg<u32, _SM1_EXECCTRL>>

pub fn side_en(&mut self) -> SIDE_EN_W<'_>

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<'_>

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

pub fn jmp_pin(&mut self) -> JMP_PIN_W<'_>

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<'_>

Bits 19:23 - Which data bit to use for inline OUT enable

pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<'_>

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

pub fn out_sticky(&mut self) -> OUT_STICKY_W<'_>

Bit 17 - Continuously assert the most recent OUT/SET to the pins

pub fn wrap_top(&mut self) -> WRAP_TOP_W<'_>

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<'_>

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

pub fn status_sel(&mut self) -> STATUS_SEL_W<'_>

Bit 4 - Comparison used for the MOV x, STATUS instruction.

pub fn status_n(&mut self) -> STATUS_N_W<'_>

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

impl W<u32, Reg<u32, _SM1_SHIFTCTRL>>

pub fn fjoin_rx(&mut self) -> FJOIN_RX_W<'_>

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn fjoin_tx(&mut self) -> FJOIN_TX_W<'_>

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn pull_thresh(&mut self) -> PULL_THRESH_W<'_>

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

pub fn push_thresh(&mut self) -> PUSH_THRESH_W<'_>

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W<'_>

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W<'_>

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

pub fn autopull(&mut self) -> AUTOPULL_W<'_>

Bit 17 - Pull automatically when the output shift register is emptied

pub fn autopush(&mut self) -> AUTOPUSH_W<'_>

Bit 16 - Push automatically when the input shift register is filled

impl W<u32, Reg<u32, _SM1_INSTR>>

pub fn sm1_instr(&mut self) -> SM1_INSTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SM1_PINCTRL>>

pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<'_>

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

pub fn set_count(&mut self) -> SET_COUNT_W<'_>

Bits 26:28 - The number of pins asserted by a SET. Max of 5

pub fn out_count(&mut self) -> OUT_COUNT_W<'_>

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

pub fn in_base(&mut self) -> IN_BASE_W<'_>

Bits 15:19 - The virtual pin corresponding to IN bit 0

pub fn sideset_base(&mut self) -> SIDESET_BASE_W<'_>

Bits 10:14 - The virtual pin corresponding to delay field bit 0

pub fn set_base(&mut self) -> SET_BASE_W<'_>

Bits 5:9 - The virtual pin corresponding to SET bit 0

pub fn out_base(&mut self) -> OUT_BASE_W<'_>

Bits 0:4 - The virtual pin corresponding to OUT bit 0

impl W<u32, Reg<u32, _SM2_CLKDIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 8:15 - Fractional part of clock divider

impl W<u32, Reg<u32, _SM2_EXECCTRL>>

pub fn side_en(&mut self) -> SIDE_EN_W<'_>

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<'_>

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

pub fn jmp_pin(&mut self) -> JMP_PIN_W<'_>

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<'_>

Bits 19:23 - Which data bit to use for inline OUT enable

pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<'_>

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

pub fn out_sticky(&mut self) -> OUT_STICKY_W<'_>

Bit 17 - Continuously assert the most recent OUT/SET to the pins

pub fn wrap_top(&mut self) -> WRAP_TOP_W<'_>

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<'_>

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

pub fn status_sel(&mut self) -> STATUS_SEL_W<'_>

Bit 4 - Comparison used for the MOV x, STATUS instruction.

pub fn status_n(&mut self) -> STATUS_N_W<'_>

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

impl W<u32, Reg<u32, _SM2_SHIFTCTRL>>

pub fn fjoin_rx(&mut self) -> FJOIN_RX_W<'_>

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn fjoin_tx(&mut self) -> FJOIN_TX_W<'_>

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn pull_thresh(&mut self) -> PULL_THRESH_W<'_>

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

pub fn push_thresh(&mut self) -> PUSH_THRESH_W<'_>

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W<'_>

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W<'_>

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

pub fn autopull(&mut self) -> AUTOPULL_W<'_>

Bit 17 - Pull automatically when the output shift register is emptied

pub fn autopush(&mut self) -> AUTOPUSH_W<'_>

Bit 16 - Push automatically when the input shift register is filled

impl W<u32, Reg<u32, _SM2_INSTR>>

pub fn sm2_instr(&mut self) -> SM2_INSTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SM2_PINCTRL>>

pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<'_>

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

pub fn set_count(&mut self) -> SET_COUNT_W<'_>

Bits 26:28 - The number of pins asserted by a SET. Max of 5

pub fn out_count(&mut self) -> OUT_COUNT_W<'_>

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

pub fn in_base(&mut self) -> IN_BASE_W<'_>

Bits 15:19 - The virtual pin corresponding to IN bit 0

pub fn sideset_base(&mut self) -> SIDESET_BASE_W<'_>

Bits 10:14 - The virtual pin corresponding to delay field bit 0

pub fn set_base(&mut self) -> SET_BASE_W<'_>

Bits 5:9 - The virtual pin corresponding to SET bit 0

pub fn out_base(&mut self) -> OUT_BASE_W<'_>

Bits 0:4 - The virtual pin corresponding to OUT bit 0

impl W<u32, Reg<u32, _SM3_CLKDIV>>

pub fn int(&mut self) -> INT_W<'_>

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

pub fn frac(&mut self) -> FRAC_W<'_>

Bits 8:15 - Fractional part of clock divider

impl W<u32, Reg<u32, _SM3_EXECCTRL>>

pub fn side_en(&mut self) -> SIDE_EN_W<'_>

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<'_>

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

pub fn jmp_pin(&mut self) -> JMP_PIN_W<'_>

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<'_>

Bits 19:23 - Which data bit to use for inline OUT enable

pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<'_>

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

pub fn out_sticky(&mut self) -> OUT_STICKY_W<'_>

Bit 17 - Continuously assert the most recent OUT/SET to the pins

pub fn wrap_top(&mut self) -> WRAP_TOP_W<'_>

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<'_>

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

pub fn status_sel(&mut self) -> STATUS_SEL_W<'_>

Bit 4 - Comparison used for the MOV x, STATUS instruction.

pub fn status_n(&mut self) -> STATUS_N_W<'_>

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

impl W<u32, Reg<u32, _SM3_SHIFTCTRL>>

pub fn fjoin_rx(&mut self) -> FJOIN_RX_W<'_>

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn fjoin_tx(&mut self) -> FJOIN_TX_W<'_>

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

pub fn pull_thresh(&mut self) -> PULL_THRESH_W<'_>

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

pub fn push_thresh(&mut self) -> PUSH_THRESH_W<'_>

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W<'_>

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W<'_>

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

pub fn autopull(&mut self) -> AUTOPULL_W<'_>

Bit 17 - Pull automatically when the output shift register is emptied

pub fn autopush(&mut self) -> AUTOPUSH_W<'_>

Bit 16 - Push automatically when the input shift register is filled

impl W<u32, Reg<u32, _SM3_INSTR>>

pub fn sm3_instr(&mut self) -> SM3_INSTR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SM3_PINCTRL>>

pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<'_>

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

pub fn set_count(&mut self) -> SET_COUNT_W<'_>

Bits 26:28 - The number of pins asserted by a SET. Max of 5

pub fn out_count(&mut self) -> OUT_COUNT_W<'_>

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

pub fn in_base(&mut self) -> IN_BASE_W<'_>

Bits 15:19 - The virtual pin corresponding to IN bit 0

pub fn sideset_base(&mut self) -> SIDESET_BASE_W<'_>

Bits 10:14 - The virtual pin corresponding to delay field bit 0

pub fn set_base(&mut self) -> SET_BASE_W<'_>

Bits 5:9 - The virtual pin corresponding to SET bit 0

pub fn out_base(&mut self) -> OUT_BASE_W<'_>

Bits 0:4 - The virtual pin corresponding to OUT bit 0

impl W<u32, Reg<u32, _IRQ0_INTE>>

pub fn sm3(&mut self) -> SM3_W<'_>

Bit 11

pub fn sm2(&mut self) -> SM2_W<'_>

Bit 10

pub fn sm1(&mut self) -> SM1_W<'_>

Bit 9

pub fn sm0(&mut self) -> SM0_W<'_>

Bit 8

pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<'_>

Bit 7

pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<'_>

Bit 6

pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<'_>

Bit 5

pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<'_>

Bit 4

pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<'_>

Bit 3

pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<'_>

Bit 2

pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<'_>

Bit 1

pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<'_>

Bit 0

impl W<u32, Reg<u32, _IRQ0_INTF>>

pub fn sm3(&mut self) -> SM3_W<'_>

Bit 11

pub fn sm2(&mut self) -> SM2_W<'_>

Bit 10

pub fn sm1(&mut self) -> SM1_W<'_>

Bit 9

pub fn sm0(&mut self) -> SM0_W<'_>

Bit 8

pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<'_>

Bit 7

pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<'_>

Bit 6

pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<'_>

Bit 5

pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<'_>

Bit 4

pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<'_>

Bit 3

pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<'_>

Bit 2

pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<'_>

Bit 1

pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<'_>

Bit 0

impl W<u32, Reg<u32, _IRQ1_INTE>>

pub fn sm3(&mut self) -> SM3_W<'_>

Bit 11

pub fn sm2(&mut self) -> SM2_W<'_>

Bit 10

pub fn sm1(&mut self) -> SM1_W<'_>

Bit 9

pub fn sm0(&mut self) -> SM0_W<'_>

Bit 8

pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<'_>

Bit 7

pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<'_>

Bit 6

pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<'_>

Bit 5

pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<'_>

Bit 4

pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<'_>

Bit 3

pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<'_>

Bit 2

pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<'_>

Bit 1

pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<'_>

Bit 0

impl W<u32, Reg<u32, _IRQ1_INTF>>

pub fn sm3(&mut self) -> SM3_W<'_>

Bit 11

pub fn sm2(&mut self) -> SM2_W<'_>

Bit 10

pub fn sm1(&mut self) -> SM1_W<'_>

Bit 9

pub fn sm0(&mut self) -> SM0_W<'_>

Bit 8

pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<'_>

Bit 7

pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<'_>

Bit 6

pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<'_>

Bit 5

pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<'_>

Bit 4

pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<'_>

Bit 3

pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<'_>

Bit 2

pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<'_>

Bit 1

pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<'_>

Bit 0

impl W<u32, Reg<u32, _GPIO_OUT>>

pub fn gpio_out(&mut self) -> GPIO_OUT_W<'_>

Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29.\n Reading back gives the last value written, NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

impl W<u32, Reg<u32, _GPIO_OUT_SET>>

pub fn gpio_out_set(&mut self) -> GPIO_OUT_SET_W<'_>

Bits 0:29 - Perform an atomic bit-set on GPIO_OUT, i.e. GPIO_OUT |= wdata

impl W<u32, Reg<u32, _GPIO_OUT_CLR>>

pub fn gpio_out_clr(&mut self) -> GPIO_OUT_CLR_W<'_>

Bits 0:29 - Perform an atomic bit-clear on GPIO_OUT, i.e. GPIO_OUT &= ~wdata

impl W<u32, Reg<u32, _GPIO_OUT_XOR>>

pub fn gpio_out_xor(&mut self) -> GPIO_OUT_XOR_W<'_>

Bits 0:29 - Perform an atomic bitwise XOR on GPIO_OUT, i.e. GPIO_OUT ^= wdata

impl W<u32, Reg<u32, _GPIO_OE>>

pub fn gpio_oe(&mut self) -> GPIO_OE_W<'_>

Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

impl W<u32, Reg<u32, _GPIO_OE_SET>>

pub fn gpio_oe_set(&mut self) -> GPIO_OE_SET_W<'_>

Bits 0:29 - Perform an atomic bit-set on GPIO_OE, i.e. GPIO_OE |= wdata

impl W<u32, Reg<u32, _GPIO_OE_CLR>>

pub fn gpio_oe_clr(&mut self) -> GPIO_OE_CLR_W<'_>

Bits 0:29 - Perform an atomic bit-clear on GPIO_OE, i.e. GPIO_OE &= ~wdata

impl W<u32, Reg<u32, _GPIO_OE_XOR>>

pub fn gpio_oe_xor(&mut self) -> GPIO_OE_XOR_W<'_>

Bits 0:29 - Perform an atomic bitwise XOR on GPIO_OE, i.e. GPIO_OE ^= wdata

impl W<u32, Reg<u32, _GPIO_HI_OUT>>

pub fn gpio_hi_out(&mut self) -> GPIO_HI_OUT_W<'_>

Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5.\n Reading back gives the last value written, NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

impl W<u32, Reg<u32, _GPIO_HI_OUT_SET>>

pub fn gpio_hi_out_set(&mut self) -> GPIO_HI_OUT_SET_W<'_>

Bits 0:5 - Perform an atomic bit-set on GPIO_HI_OUT, i.e. GPIO_HI_OUT |= wdata

impl W<u32, Reg<u32, _GPIO_HI_OUT_CLR>>

pub fn gpio_hi_out_clr(&mut self) -> GPIO_HI_OUT_CLR_W<'_>

Bits 0:5 - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. GPIO_HI_OUT &= ~wdata

impl W<u32, Reg<u32, _GPIO_HI_OUT_XOR>>

pub fn gpio_hi_out_xor(&mut self) -> GPIO_HI_OUT_XOR_W<'_>

Bits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. GPIO_HI_OUT ^= wdata

impl W<u32, Reg<u32, _GPIO_HI_OE>>

pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W<'_>

Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

impl W<u32, Reg<u32, _GPIO_HI_OE_SET>>

pub fn gpio_hi_oe_set(&mut self) -> GPIO_HI_OE_SET_W<'_>

Bits 0:5 - Perform an atomic bit-set on GPIO_HI_OE, i.e. GPIO_HI_OE |= wdata

impl W<u32, Reg<u32, _GPIO_HI_OE_CLR>>

pub fn gpio_hi_oe_clr(&mut self) -> GPIO_HI_OE_CLR_W<'_>

Bits 0:5 - Perform an atomic bit-clear on GPIO_HI_OE, i.e. GPIO_HI_OE &= ~wdata

impl W<u32, Reg<u32, _GPIO_HI_OE_XOR>>

pub fn gpio_hi_oe_xor(&mut self) -> GPIO_HI_OE_XOR_W<'_>

Bits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. GPIO_HI_OE ^= wdata

impl W<u32, Reg<u32, _FIFO_ST>>

pub fn roe(&mut self) -> ROE_W<'_>

Bit 3 - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.

pub fn wof(&mut self) -> WOF_W<'_>

Bit 2 - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.

impl W<u32, Reg<u32, _INTERP0_CTRL_LANE0>>

pub fn blend(&mut self) -> BLEND_W<'_>

Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled:\n - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n 0 and 255/256ths)\n - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

pub fn force_msb(&mut self) -> FORCE_MSB_W<'_>

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

pub fn add_raw(&mut self) -> ADD_RAW_W<'_>

Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

pub fn cross_result(&mut self) -> CROSS_RESULT_W<'_>

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

pub fn cross_input(&mut self) -> CROSS_INPUT_W<'_>

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

pub fn signed(&mut self) -> SIGNED_W<'_>

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

pub fn mask_msb(&mut self) -> MASK_MSB_W<'_>

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

pub fn mask_lsb(&mut self) -> MASK_LSB_W<'_>

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

pub fn shift(&mut self) -> SHIFT_W<'_>

Bits 0:4 - Logical right-shift applied to accumulator before masking

impl W<u32, Reg<u32, _INTERP0_CTRL_LANE1>>

pub fn force_msb(&mut self) -> FORCE_MSB_W<'_>

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

pub fn add_raw(&mut self) -> ADD_RAW_W<'_>

Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

pub fn cross_result(&mut self) -> CROSS_RESULT_W<'_>

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

pub fn cross_input(&mut self) -> CROSS_INPUT_W<'_>

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

pub fn signed(&mut self) -> SIGNED_W<'_>

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

pub fn mask_msb(&mut self) -> MASK_MSB_W<'_>

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

pub fn mask_lsb(&mut self) -> MASK_LSB_W<'_>

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

pub fn shift(&mut self) -> SHIFT_W<'_>

Bits 0:4 - Logical right-shift applied to accumulator before masking

impl W<u32, Reg<u32, _INTERP0_ACCUM0_ADD>>

pub fn interp0_accum0_add(&mut self) -> INTERP0_ACCUM0_ADD_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _INTERP0_ACCUM1_ADD>>

pub fn interp0_accum1_add(&mut self) -> INTERP0_ACCUM1_ADD_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _INTERP1_CTRL_LANE0>>

pub fn clamp(&mut self) -> CLAMP_W<'_>

Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled:\n - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n BASE0 and an upper bound of BASE1.\n - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

pub fn force_msb(&mut self) -> FORCE_MSB_W<'_>

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

pub fn add_raw(&mut self) -> ADD_RAW_W<'_>

Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

pub fn cross_result(&mut self) -> CROSS_RESULT_W<'_>

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

pub fn cross_input(&mut self) -> CROSS_INPUT_W<'_>

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

pub fn signed(&mut self) -> SIGNED_W<'_>

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

pub fn mask_msb(&mut self) -> MASK_MSB_W<'_>

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

pub fn mask_lsb(&mut self) -> MASK_LSB_W<'_>

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

pub fn shift(&mut self) -> SHIFT_W<'_>

Bits 0:4 - Logical right-shift applied to accumulator before masking

impl W<u32, Reg<u32, _INTERP1_CTRL_LANE1>>

pub fn force_msb(&mut self) -> FORCE_MSB_W<'_>

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

pub fn add_raw(&mut self) -> ADD_RAW_W<'_>

Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

pub fn cross_result(&mut self) -> CROSS_RESULT_W<'_>

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

pub fn cross_input(&mut self) -> CROSS_INPUT_W<'_>

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

pub fn signed(&mut self) -> SIGNED_W<'_>

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

pub fn mask_msb(&mut self) -> MASK_MSB_W<'_>

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

pub fn mask_lsb(&mut self) -> MASK_LSB_W<'_>

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

pub fn shift(&mut self) -> SHIFT_W<'_>

Bits 0:4 - Logical right-shift applied to accumulator before masking

impl W<u32, Reg<u32, _INTERP1_ACCUM0_ADD>>

pub fn interp1_accum0_add(&mut self) -> INTERP1_ACCUM0_ADD_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _INTERP1_ACCUM1_ADD>>

pub fn interp1_accum1_add(&mut self) -> INTERP1_ACCUM1_ADD_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _SYST_CSR>>

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n Selects the SysTick timer clock source:\n 0 = External reference clock.\n 1 = Processor clock.

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - Enables SysTick exception request:\n 0 = Counting down to zero does not assert the SysTick exception request.\n 1 = Counting down to zero to asserts the SysTick exception request.

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable SysTick counter:\n 0 = Counter disabled.\n 1 = Counter enabled.

impl W<u32, Reg<u32, _SYST_RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0.

impl W<u32, Reg<u32, _SYST_CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.

impl W<u32, Reg<u32, _NVIC_ISER>>

pub fn setena(&mut self) -> SETENA_W<'_>

Bits 0:31 - Interrupt set-enable bits.\n Write:\n 0 = No effect.\n 1 = Enable interrupt.\n Read:\n 0 = Interrupt disabled.\n 1 = Interrupt enabled.

impl W<u32, Reg<u32, _NVIC_ICER>>

pub fn clrena(&mut self) -> CLRENA_W<'_>

Bits 0:31 - Interrupt clear-enable bits.\n Write:\n 0 = No effect.\n 1 = Disable interrupt.\n Read:\n 0 = Interrupt disabled.\n 1 = Interrupt enabled.

impl W<u32, Reg<u32, _NVIC_ISPR>>

pub fn setpend(&mut self) -> SETPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.\n Write:\n 0 = No effect.\n 1 = Changes interrupt state to pending.\n Read:\n 0 = Interrupt is not pending.\n 1 = Interrupt is pending.\n Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n An interrupt that is pending has no effect.\n A disabled interrupt sets the state of that interrupt to pending.

impl W<u32, Reg<u32, _NVIC_ICPR>>

pub fn clrpend(&mut self) -> CLRPEND_W<'_>

Bits 0:31 - Interrupt clear-pending bits.\n Write:\n 0 = No effect.\n 1 = Removes pending state and interrupt.\n Read:\n 0 = Interrupt is not pending.\n 1 = Interrupt is pending.

impl W<u32, Reg<u32, _NVIC_IPR0>>

pub fn ip_3(&mut self) -> IP_3_W<'_>

Bits 30:31 - Priority of interrupt 3

pub fn ip_2(&mut self) -> IP_2_W<'_>

Bits 22:23 - Priority of interrupt 2

pub fn ip_1(&mut self) -> IP_1_W<'_>

Bits 14:15 - Priority of interrupt 1

pub fn ip_0(&mut self) -> IP_0_W<'_>

Bits 6:7 - Priority of interrupt 0

impl W<u32, Reg<u32, _NVIC_IPR1>>

pub fn ip_7(&mut self) -> IP_7_W<'_>

Bits 30:31 - Priority of interrupt 7

pub fn ip_6(&mut self) -> IP_6_W<'_>

Bits 22:23 - Priority of interrupt 6

pub fn ip_5(&mut self) -> IP_5_W<'_>

Bits 14:15 - Priority of interrupt 5

pub fn ip_4(&mut self) -> IP_4_W<'_>

Bits 6:7 - Priority of interrupt 4

impl W<u32, Reg<u32, _NVIC_IPR2>>

pub fn ip_11(&mut self) -> IP_11_W<'_>

Bits 30:31 - Priority of interrupt 11

pub fn ip_10(&mut self) -> IP_10_W<'_>

Bits 22:23 - Priority of interrupt 10

pub fn ip_9(&mut self) -> IP_9_W<'_>

Bits 14:15 - Priority of interrupt 9

pub fn ip_8(&mut self) -> IP_8_W<'_>

Bits 6:7 - Priority of interrupt 8

impl W<u32, Reg<u32, _NVIC_IPR3>>

pub fn ip_15(&mut self) -> IP_15_W<'_>

Bits 30:31 - Priority of interrupt 15

pub fn ip_14(&mut self) -> IP_14_W<'_>

Bits 22:23 - Priority of interrupt 14

pub fn ip_13(&mut self) -> IP_13_W<'_>

Bits 14:15 - Priority of interrupt 13

pub fn ip_12(&mut self) -> IP_12_W<'_>

Bits 6:7 - Priority of interrupt 12

impl W<u32, Reg<u32, _NVIC_IPR4>>

pub fn ip_19(&mut self) -> IP_19_W<'_>

Bits 30:31 - Priority of interrupt 19

pub fn ip_18(&mut self) -> IP_18_W<'_>

Bits 22:23 - Priority of interrupt 18

pub fn ip_17(&mut self) -> IP_17_W<'_>

Bits 14:15 - Priority of interrupt 17

pub fn ip_16(&mut self) -> IP_16_W<'_>

Bits 6:7 - Priority of interrupt 16

impl W<u32, Reg<u32, _NVIC_IPR5>>

pub fn ip_23(&mut self) -> IP_23_W<'_>

Bits 30:31 - Priority of interrupt 23

pub fn ip_22(&mut self) -> IP_22_W<'_>

Bits 22:23 - Priority of interrupt 22

pub fn ip_21(&mut self) -> IP_21_W<'_>

Bits 14:15 - Priority of interrupt 21

pub fn ip_20(&mut self) -> IP_20_W<'_>

Bits 6:7 - Priority of interrupt 20

impl W<u32, Reg<u32, _NVIC_IPR6>>

pub fn ip_27(&mut self) -> IP_27_W<'_>

Bits 30:31 - Priority of interrupt 27

pub fn ip_26(&mut self) -> IP_26_W<'_>

Bits 22:23 - Priority of interrupt 26

pub fn ip_25(&mut self) -> IP_25_W<'_>

Bits 14:15 - Priority of interrupt 25

pub fn ip_24(&mut self) -> IP_24_W<'_>

Bits 6:7 - Priority of interrupt 24

impl W<u32, Reg<u32, _NVIC_IPR7>>

pub fn ip_31(&mut self) -> IP_31_W<'_>

Bits 30:31 - Priority of interrupt 31

pub fn ip_30(&mut self) -> IP_30_W<'_>

Bits 22:23 - Priority of interrupt 30

pub fn ip_29(&mut self) -> IP_29_W<'_>

Bits 14:15 - Priority of interrupt 29

pub fn ip_28(&mut self) -> IP_28_W<'_>

Bits 6:7 - Priority of interrupt 28

impl W<u32, Reg<u32, _ICSR>>

pub fn nmipendset(&mut self) -> NMIPENDSET_W<'_>

Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n NMI set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes NMI exception state to pending.\n Read:\n 0 = NMI exception is not pending.\n 1 = NMI exception is pending.\n Because NMI is the highest-priority exception, normally the processor enters the NMI\n exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n NMI signal is reasserted while the processor is executing that handler.

pub fn pendsvset(&mut self) -> PENDSVSET_W<'_>

Bit 28 - PendSV set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes PendSV exception state to pending.\n Read:\n 0 = PendSV exception is not pending.\n 1 = PendSV exception is pending.\n Writing 1 to this bit is the only way to set the PendSV exception state to pending.

pub fn pendsvclr(&mut self) -> PENDSVCLR_W<'_>

Bit 27 - PendSV clear-pending bit.\n Write:\n 0 = No effect.\n 1 = Removes the pending state from the PendSV exception.

pub fn pendstset(&mut self) -> PENDSTSET_W<'_>

Bit 26 - SysTick exception set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes SysTick exception state to pending.\n Read:\n 0 = SysTick exception is not pending.\n 1 = SysTick exception is pending.

pub fn pendstclr(&mut self) -> PENDSTCLR_W<'_>

Bit 25 - SysTick exception clear-pending bit.\n Write:\n 0 = No effect.\n 1 = Removes the pending state from the SysTick exception.\n This bit is WO. On a register read its value is Unknown.

impl W<u32, Reg<u32, _VTOR>>

pub fn tbloff(&mut self) -> TBLOFF_W<'_>

Bits 8:31 - Bits [31:8] of the indicate the vector table offset address.

impl W<u32, Reg<u32, _AIRCR>>

pub fn vectkey(&mut self) -> VECTKEY_W<'_>

Bits 16:31 - Register key:\n Reads as Unknown\n On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.

pub fn sysresetreq(&mut self) -> SYSRESETREQ_W<'_>

Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.

pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W<'_>

Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.

impl W<u32, Reg<u32, _SCR>>

pub fn sevonpend(&mut self) -> SEVONPEND_W<'_>

Bit 4 - Send Event on Pending bit:\n 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n processor is not waiting for an event, the event is registered and affects the next WFE.\n The processor also wakes up on execution of an SEV instruction or an external event.

pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<'_>

Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode:\n 0 = Sleep.\n 1 = Deep sleep.

pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<'_>

Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n 0 = Do not sleep when returning to Thread mode.\n 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

impl W<u32, Reg<u32, _SHPR2>>

pub fn pri_11(&mut self) -> PRI_11_W<'_>

Bits 30:31 - Priority of system handler 11, SVCall

impl W<u32, Reg<u32, _SHPR3>>

pub fn pri_15(&mut self) -> PRI_15_W<'_>

Bits 30:31 - Priority of system handler 15, SysTick

pub fn pri_14(&mut self) -> PRI_14_W<'_>

Bits 22:23 - Priority of system handler 14, PendSV

impl W<u32, Reg<u32, _SHCSR>>

pub fn svcallpended(&mut self) -> SVCALLPENDED_W<'_>

Bit 15 - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.

impl W<u32, Reg<u32, _MPU_CTRL>>

pub fn privdefena(&mut self) -> PRIVDEFENA_W<'_>

Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n covered by any enabled region causes a fault.\n 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.

pub fn hfnmiena(&mut self) -> HFNMIENA_W<'_>

Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n When the MPU is enabled:\n 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n 1 = the MPU is enabled during HardFault and NMI handlers.

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n 0 = MPU disabled.\n 1 = MPU enabled.

impl W<u32, Reg<u32, _MPU_RNR>>

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n The MPU supports 8 memory regions, so the permitted values of this field are 0-7.

impl W<u32, Reg<u32, _MPU_RBAR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 8:31 - Base address of the region.

pub fn valid(&mut self) -> VALID_W<'_>

Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n Write:\n 0 = MPU_RNR not changed, and the processor:\n Updates the base address for the region specified in the MPU_RNR.\n Ignores the value of the REGION field.\n 1 = The processor:\n Updates the value of the MPU_RNR to the value of the REGION field.\n Updates the base address for the region specified in the REGION field.\n Always reads as zero.

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:3 - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.

impl W<u32, Reg<u32, _MPU_RASR>>

pub fn attrs(&mut self) -> ATTRS_W<'_>

Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control.\n 28 = XN: Instruction access disable bit:\n 0 = Instruction fetches enabled.\n 1 = Instruction fetches disabled.\n 26:24 = AP: Access permission field\n 18 = S: Shareable bit\n 17 = C: Cacheable bit\n 16 = B: Bufferable bit

pub fn srd(&mut self) -> SRD_W<'_>

Bits 8:15 - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.

pub fn size(&mut self) -> SIZE_W<'_>

Bits 1:5 - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enables the region.