[−][src]Struct rp2040::pwm::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ch0_csr: CH0_CSR,
    pub ch0_div: CH0_DIV,
    pub ch0_ctr: CH0_CTR,
    pub ch0_cc: CH0_CC,
    pub ch0_top: CH0_TOP,
    pub ch1_csr: CH1_CSR,
    pub ch1_div: CH1_DIV,
    pub ch1_ctr: CH1_CTR,
    pub ch1_cc: CH1_CC,
    pub ch1_top: CH1_TOP,
    pub ch2_csr: CH2_CSR,
    pub ch2_div: CH2_DIV,
    pub ch2_ctr: CH2_CTR,
    pub ch2_cc: CH2_CC,
    pub ch2_top: CH2_TOP,
    pub ch3_csr: CH3_CSR,
    pub ch3_div: CH3_DIV,
    pub ch3_ctr: CH3_CTR,
    pub ch3_cc: CH3_CC,
    pub ch3_top: CH3_TOP,
    pub ch4_csr: CH4_CSR,
    pub ch4_div: CH4_DIV,
    pub ch4_ctr: CH4_CTR,
    pub ch4_cc: CH4_CC,
    pub ch4_top: CH4_TOP,
    pub ch5_csr: CH5_CSR,
    pub ch5_div: CH5_DIV,
    pub ch5_ctr: CH5_CTR,
    pub ch5_cc: CH5_CC,
    pub ch5_top: CH5_TOP,
    pub ch6_csr: CH6_CSR,
    pub ch6_div: CH6_DIV,
    pub ch6_ctr: CH6_CTR,
    pub ch6_cc: CH6_CC,
    pub ch6_top: CH6_TOP,
    pub ch7_csr: CH7_CSR,
    pub ch7_div: CH7_DIV,
    pub ch7_ctr: CH7_CTR,
    pub ch7_cc: CH7_CC,
    pub ch7_top: CH7_TOP,
    pub en: EN,
    pub intr: INTR,
    pub inte: INTE,
    pub intf: INTF,
    pub ints: INTS,
}

Register block

Fields

ch0_csr: CH0_CSR

0x00 - Control and status register

ch0_div: CH0_DIV

0x04 - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch0_ctr: CH0_CTR

0x08 - Direct access to the PWM counter

ch0_cc: CH0_CC

0x0c - Counter compare values

ch0_top: CH0_TOP

0x10 - Counter wrap value

ch1_csr: CH1_CSR

0x14 - Control and status register

ch1_div: CH1_DIV

0x18 - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch1_ctr: CH1_CTR

0x1c - Direct access to the PWM counter

ch1_cc: CH1_CC

0x20 - Counter compare values

ch1_top: CH1_TOP

0x24 - Counter wrap value

ch2_csr: CH2_CSR

0x28 - Control and status register

ch2_div: CH2_DIV

0x2c - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch2_ctr: CH2_CTR

0x30 - Direct access to the PWM counter

ch2_cc: CH2_CC

0x34 - Counter compare values

ch2_top: CH2_TOP

0x38 - Counter wrap value

ch3_csr: CH3_CSR

0x3c - Control and status register

ch3_div: CH3_DIV

0x40 - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch3_ctr: CH3_CTR

0x44 - Direct access to the PWM counter

ch3_cc: CH3_CC

0x48 - Counter compare values

ch3_top: CH3_TOP

0x4c - Counter wrap value

ch4_csr: CH4_CSR

0x50 - Control and status register

ch4_div: CH4_DIV

0x54 - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch4_ctr: CH4_CTR

0x58 - Direct access to the PWM counter

ch4_cc: CH4_CC

0x5c - Counter compare values

ch4_top: CH4_TOP

0x60 - Counter wrap value

ch5_csr: CH5_CSR

0x64 - Control and status register

ch5_div: CH5_DIV

0x68 - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch5_ctr: CH5_CTR

0x6c - Direct access to the PWM counter

ch5_cc: CH5_CC

0x70 - Counter compare values

ch5_top: CH5_TOP

0x74 - Counter wrap value

ch6_csr: CH6_CSR

0x78 - Control and status register

ch6_div: CH6_DIV

0x7c - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch6_ctr: CH6_CTR

0x80 - Direct access to the PWM counter

ch6_cc: CH6_CC

0x84 - Counter compare values

ch6_top: CH6_TOP

0x88 - Counter wrap value

ch7_csr: CH7_CSR

0x8c - Control and status register

ch7_div: CH7_DIV

0x90 - INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.

ch7_ctr: CH7_CTR

0x94 - Direct access to the PWM counter

ch7_cc: CH7_CC

0x98 - Counter compare values

ch7_top: CH7_TOP

0x9c - Counter wrap value

en: EN

0xa0 - This register aliases the CSR_EN bits for all channels.\n Writing to this register allows multiple channels to be enabled\n or disabled simultaneously, so they can run in perfect sync.\n For each channel, there is only one physical EN register bit,\n which can be accessed through here or CHx_CSR.

intr: INTR

0xa4 - Raw Interrupts

inte: INTE

0xa8 - Interrupt Enable

intf: INTF

0xac - Interrupt Force

ints: INTS

0xb0 - Interrupt status after masking & forcing

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