Module rp2040::pwm

Simple PWM

Modules

ch0_cc	Counter compare values
ch0_csr	Control and status register
ch0_ctr	Direct access to the PWM counter
ch0_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch0_top	Counter wrap value
ch1_cc	Counter compare values
ch1_csr	Control and status register
ch1_ctr	Direct access to the PWM counter
ch1_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch1_top	Counter wrap value
ch2_cc	Counter compare values
ch2_csr	Control and status register
ch2_ctr	Direct access to the PWM counter
ch2_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch2_top	Counter wrap value
ch3_cc	Counter compare values
ch3_csr	Control and status register
ch3_ctr	Direct access to the PWM counter
ch3_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch3_top	Counter wrap value
ch4_cc	Counter compare values
ch4_csr	Control and status register
ch4_ctr	Direct access to the PWM counter
ch4_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch4_top	Counter wrap value
ch5_cc	Counter compare values
ch5_csr	Control and status register
ch5_ctr	Direct access to the PWM counter
ch5_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch5_top	Counter wrap value
ch6_cc	Counter compare values
ch6_csr	Control and status register
ch6_ctr	Direct access to the PWM counter
ch6_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch6_top	Counter wrap value
ch7_cc	Counter compare values
ch7_csr	Control and status register
ch7_ctr	Direct access to the PWM counter
ch7_div	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
ch7_top	Counter wrap value
en	This register aliases the CSR_EN bits for all channels.\n Writing to this register allows multiple channels to be enabled\n or disabled simultaneously, so they can run in perfect sync.\n For each channel, there is only one physical EN register bit,\n which can be accessed through here or CHx_CSR.
inte	Interrupt Enable
intf	Interrupt Force
intr	Raw Interrupts
ints	Interrupt status after masking & forcing

Structs

RegisterBlock

Register block

Type Definitions

CH0_CC	Counter compare values
CH0_CSR	Control and status register
CH0_CTR	Direct access to the PWM counter
CH0_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH0_TOP	Counter wrap value
CH1_CC	Counter compare values
CH1_CSR	Control and status register
CH1_CTR	Direct access to the PWM counter
CH1_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH1_TOP	Counter wrap value
CH2_CC	Counter compare values
CH2_CSR	Control and status register
CH2_CTR	Direct access to the PWM counter
CH2_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH2_TOP	Counter wrap value
CH3_CC	Counter compare values
CH3_CSR	Control and status register
CH3_CTR	Direct access to the PWM counter
CH3_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH3_TOP	Counter wrap value
CH4_CC	Counter compare values
CH4_CSR	Control and status register
CH4_CTR	Direct access to the PWM counter
CH4_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH4_TOP	Counter wrap value
CH5_CC	Counter compare values
CH5_CSR	Control and status register
CH5_CTR	Direct access to the PWM counter
CH5_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH5_TOP	Counter wrap value
CH6_CC	Counter compare values
CH6_CSR	Control and status register
CH6_CTR	Direct access to the PWM counter
CH6_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH6_TOP	Counter wrap value
CH7_CC	Counter compare values
CH7_CSR	Control and status register
CH7_CTR	Direct access to the PWM counter
CH7_DIV	INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta.
CH7_TOP	Counter wrap value
EN	This register aliases the CSR_EN bits for all channels.\n Writing to this register allows multiple channels to be enabled\n or disabled simultaneously, so they can run in perfect sync.\n For each channel, there is only one physical EN register bit,\n which can be accessed through here or CHx_CSR.
INTE	Interrupt Enable
INTF	Interrupt Force
INTR	Raw Interrupts
INTS	Interrupt status after masking & forcing