[][src]Type Definition rp2040::dma::intr::R

type R = R<u32, INTR>;

Reader of register INTR

Implementations

impl R[src]

pub fn intr(&self) -> INTR_R[src]

Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.