[][src]Module rp2040::dma

DMA with separate read and write masters

Modules

ch0_al1_ctrl

Alias for channel 0 CTRL register

ch0_al1_read_addr

Alias for channel 0 READ_ADDR register

ch0_al1_trans_count_trig

Alias for channel 0 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch0_al1_write_addr

Alias for channel 0 WRITE_ADDR register

ch0_al2_ctrl

Alias for channel 0 CTRL register

ch0_al2_read_addr

Alias for channel 0 READ_ADDR register

ch0_al2_trans_count

Alias for channel 0 TRANS_COUNT register

ch0_al2_write_addr_trig

Alias for channel 0 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch0_al3_ctrl

Alias for channel 0 CTRL register

ch0_al3_read_addr_trig

Alias for channel 0 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch0_al3_trans_count

Alias for channel 0 TRANS_COUNT register

ch0_al3_write_addr

Alias for channel 0 WRITE_ADDR register

ch0_ctrl_trig

DMA Channel 0 Control and Status

ch0_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch0_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch0_read_addr

DMA Channel 0 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch0_trans_count

DMA Channel 0 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch0_write_addr

DMA Channel 0 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch1_al1_ctrl

Alias for channel 1 CTRL register

ch1_al1_read_addr

Alias for channel 1 READ_ADDR register

ch1_al1_trans_count_trig

Alias for channel 1 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch1_al1_write_addr

Alias for channel 1 WRITE_ADDR register

ch1_al2_ctrl

Alias for channel 1 CTRL register

ch1_al2_read_addr

Alias for channel 1 READ_ADDR register

ch1_al2_trans_count

Alias for channel 1 TRANS_COUNT register

ch1_al2_write_addr_trig

Alias for channel 1 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch1_al3_ctrl

Alias for channel 1 CTRL register

ch1_al3_read_addr_trig

Alias for channel 1 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch1_al3_trans_count

Alias for channel 1 TRANS_COUNT register

ch1_al3_write_addr

Alias for channel 1 WRITE_ADDR register

ch1_ctrl_trig

DMA Channel 1 Control and Status

ch1_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch1_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch1_read_addr

DMA Channel 1 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch1_trans_count

DMA Channel 1 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch1_write_addr

DMA Channel 1 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch2_al1_ctrl

Alias for channel 2 CTRL register

ch2_al1_read_addr

Alias for channel 2 READ_ADDR register

ch2_al1_trans_count_trig

Alias for channel 2 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch2_al1_write_addr

Alias for channel 2 WRITE_ADDR register

ch2_al2_ctrl

Alias for channel 2 CTRL register

ch2_al2_read_addr

Alias for channel 2 READ_ADDR register

ch2_al2_trans_count

Alias for channel 2 TRANS_COUNT register

ch2_al2_write_addr_trig

Alias for channel 2 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch2_al3_ctrl

Alias for channel 2 CTRL register

ch2_al3_read_addr_trig

Alias for channel 2 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch2_al3_trans_count

Alias for channel 2 TRANS_COUNT register

ch2_al3_write_addr

Alias for channel 2 WRITE_ADDR register

ch2_ctrl_trig

DMA Channel 2 Control and Status

ch2_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch2_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch2_read_addr

DMA Channel 2 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch2_trans_count

DMA Channel 2 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch2_write_addr

DMA Channel 2 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch3_al1_ctrl

Alias for channel 3 CTRL register

ch3_al1_read_addr

Alias for channel 3 READ_ADDR register

ch3_al1_trans_count_trig

Alias for channel 3 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch3_al1_write_addr

Alias for channel 3 WRITE_ADDR register

ch3_al2_ctrl

Alias for channel 3 CTRL register

ch3_al2_read_addr

Alias for channel 3 READ_ADDR register

ch3_al2_trans_count

Alias for channel 3 TRANS_COUNT register

ch3_al2_write_addr_trig

Alias for channel 3 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch3_al3_ctrl

Alias for channel 3 CTRL register

ch3_al3_read_addr_trig

Alias for channel 3 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch3_al3_trans_count

Alias for channel 3 TRANS_COUNT register

ch3_al3_write_addr

Alias for channel 3 WRITE_ADDR register

ch3_ctrl_trig

DMA Channel 3 Control and Status

ch3_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch3_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch3_read_addr

DMA Channel 3 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch3_trans_count

DMA Channel 3 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch3_write_addr

DMA Channel 3 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch4_al1_ctrl

Alias for channel 4 CTRL register

ch4_al1_read_addr

Alias for channel 4 READ_ADDR register

ch4_al1_trans_count_trig

Alias for channel 4 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch4_al1_write_addr

Alias for channel 4 WRITE_ADDR register

ch4_al2_ctrl

Alias for channel 4 CTRL register

ch4_al2_read_addr

Alias for channel 4 READ_ADDR register

ch4_al2_trans_count

Alias for channel 4 TRANS_COUNT register

ch4_al2_write_addr_trig

Alias for channel 4 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch4_al3_ctrl

Alias for channel 4 CTRL register

ch4_al3_read_addr_trig

Alias for channel 4 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch4_al3_trans_count

Alias for channel 4 TRANS_COUNT register

ch4_al3_write_addr

Alias for channel 4 WRITE_ADDR register

ch4_ctrl_trig

DMA Channel 4 Control and Status

ch4_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch4_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch4_read_addr

DMA Channel 4 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch4_trans_count

DMA Channel 4 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch4_write_addr

DMA Channel 4 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch5_al1_ctrl

Alias for channel 5 CTRL register

ch5_al1_read_addr

Alias for channel 5 READ_ADDR register

ch5_al1_trans_count_trig

Alias for channel 5 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch5_al1_write_addr

Alias for channel 5 WRITE_ADDR register

ch5_al2_ctrl

Alias for channel 5 CTRL register

ch5_al2_read_addr

Alias for channel 5 READ_ADDR register

ch5_al2_trans_count

Alias for channel 5 TRANS_COUNT register

ch5_al2_write_addr_trig

Alias for channel 5 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch5_al3_ctrl

Alias for channel 5 CTRL register

ch5_al3_read_addr_trig

Alias for channel 5 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch5_al3_trans_count

Alias for channel 5 TRANS_COUNT register

ch5_al3_write_addr

Alias for channel 5 WRITE_ADDR register

ch5_ctrl_trig

DMA Channel 5 Control and Status

ch5_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch5_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch5_read_addr

DMA Channel 5 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch5_trans_count

DMA Channel 5 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch5_write_addr

DMA Channel 5 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch6_al1_ctrl

Alias for channel 6 CTRL register

ch6_al1_read_addr

Alias for channel 6 READ_ADDR register

ch6_al1_trans_count_trig

Alias for channel 6 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch6_al1_write_addr

Alias for channel 6 WRITE_ADDR register

ch6_al2_ctrl

Alias for channel 6 CTRL register

ch6_al2_read_addr

Alias for channel 6 READ_ADDR register

ch6_al2_trans_count

Alias for channel 6 TRANS_COUNT register

ch6_al2_write_addr_trig

Alias for channel 6 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch6_al3_ctrl

Alias for channel 6 CTRL register

ch6_al3_read_addr_trig

Alias for channel 6 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch6_al3_trans_count

Alias for channel 6 TRANS_COUNT register

ch6_al3_write_addr

Alias for channel 6 WRITE_ADDR register

ch6_ctrl_trig

DMA Channel 6 Control and Status

ch6_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch6_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch6_read_addr

DMA Channel 6 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch6_trans_count

DMA Channel 6 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch6_write_addr

DMA Channel 6 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch7_al1_ctrl

Alias for channel 7 CTRL register

ch7_al1_read_addr

Alias for channel 7 READ_ADDR register

ch7_al1_trans_count_trig

Alias for channel 7 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch7_al1_write_addr

Alias for channel 7 WRITE_ADDR register

ch7_al2_ctrl

Alias for channel 7 CTRL register

ch7_al2_read_addr

Alias for channel 7 READ_ADDR register

ch7_al2_trans_count

Alias for channel 7 TRANS_COUNT register

ch7_al2_write_addr_trig

Alias for channel 7 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch7_al3_ctrl

Alias for channel 7 CTRL register

ch7_al3_read_addr_trig

Alias for channel 7 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch7_al3_trans_count

Alias for channel 7 TRANS_COUNT register

ch7_al3_write_addr

Alias for channel 7 WRITE_ADDR register

ch7_ctrl_trig

DMA Channel 7 Control and Status

ch7_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch7_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch7_read_addr

DMA Channel 7 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch7_trans_count

DMA Channel 7 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch7_write_addr

DMA Channel 7 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch8_al1_ctrl

Alias for channel 8 CTRL register

ch8_al1_read_addr

Alias for channel 8 READ_ADDR register

ch8_al1_trans_count_trig

Alias for channel 8 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch8_al1_write_addr

Alias for channel 8 WRITE_ADDR register

ch8_al2_ctrl

Alias for channel 8 CTRL register

ch8_al2_read_addr

Alias for channel 8 READ_ADDR register

ch8_al2_trans_count

Alias for channel 8 TRANS_COUNT register

ch8_al2_write_addr_trig

Alias for channel 8 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch8_al3_ctrl

Alias for channel 8 CTRL register

ch8_al3_read_addr_trig

Alias for channel 8 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch8_al3_trans_count

Alias for channel 8 TRANS_COUNT register

ch8_al3_write_addr

Alias for channel 8 WRITE_ADDR register

ch8_ctrl_trig

DMA Channel 8 Control and Status

ch8_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch8_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch8_read_addr

DMA Channel 8 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch8_trans_count

DMA Channel 8 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch8_write_addr

DMA Channel 8 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch9_al1_ctrl

Alias for channel 9 CTRL register

ch9_al1_read_addr

Alias for channel 9 READ_ADDR register

ch9_al1_trans_count_trig

Alias for channel 9 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch9_al1_write_addr

Alias for channel 9 WRITE_ADDR register

ch9_al2_ctrl

Alias for channel 9 CTRL register

ch9_al2_read_addr

Alias for channel 9 READ_ADDR register

ch9_al2_trans_count

Alias for channel 9 TRANS_COUNT register

ch9_al2_write_addr_trig

Alias for channel 9 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch9_al3_ctrl

Alias for channel 9 CTRL register

ch9_al3_read_addr_trig

Alias for channel 9 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch9_al3_trans_count

Alias for channel 9 TRANS_COUNT register

ch9_al3_write_addr

Alias for channel 9 WRITE_ADDR register

ch9_ctrl_trig

DMA Channel 9 Control and Status

ch9_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch9_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch9_read_addr

DMA Channel 9 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch9_trans_count

DMA Channel 9 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch9_write_addr

DMA Channel 9 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch10_al1_ctrl

Alias for channel 10 CTRL register

ch10_al1_read_addr

Alias for channel 10 READ_ADDR register

ch10_al1_trans_count_trig

Alias for channel 10 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch10_al1_write_addr

Alias for channel 10 WRITE_ADDR register

ch10_al2_ctrl

Alias for channel 10 CTRL register

ch10_al2_read_addr

Alias for channel 10 READ_ADDR register

ch10_al2_trans_count

Alias for channel 10 TRANS_COUNT register

ch10_al2_write_addr_trig

Alias for channel 10 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch10_al3_ctrl

Alias for channel 10 CTRL register

ch10_al3_read_addr_trig

Alias for channel 10 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch10_al3_trans_count

Alias for channel 10 TRANS_COUNT register

ch10_al3_write_addr

Alias for channel 10 WRITE_ADDR register

ch10_ctrl_trig

DMA Channel 10 Control and Status

ch10_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch10_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch10_read_addr

DMA Channel 10 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch10_trans_count

DMA Channel 10 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch10_write_addr

DMA Channel 10 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

ch11_al1_ctrl

Alias for channel 11 CTRL register

ch11_al1_read_addr

Alias for channel 11 READ_ADDR register

ch11_al1_trans_count_trig

Alias for channel 11 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch11_al1_write_addr

Alias for channel 11 WRITE_ADDR register

ch11_al2_ctrl

Alias for channel 11 CTRL register

ch11_al2_read_addr

Alias for channel 11 READ_ADDR register

ch11_al2_trans_count

Alias for channel 11 TRANS_COUNT register

ch11_al2_write_addr_trig

Alias for channel 11 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch11_al3_ctrl

Alias for channel 11 CTRL register

ch11_al3_read_addr_trig

Alias for channel 11 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

ch11_al3_trans_count

Alias for channel 11 TRANS_COUNT register

ch11_al3_write_addr

Alias for channel 11 WRITE_ADDR register

ch11_ctrl_trig

DMA Channel 11 Control and Status

ch11_dbg_ctdreq

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

ch11_dbg_tcr

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

ch11_read_addr

DMA Channel 11 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

ch11_trans_count

DMA Channel 11 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

ch11_write_addr

DMA Channel 11 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

chan_abort

Abort an in-progress transfer sequence on one or more channels

fifo_levels

Debug RAF, WAF, TDF levels

inte0

Interrupt Enables for IRQ 0

inte1

Interrupt Enables for IRQ 1

intf0

Force Interrupts

intf1

Force Interrupts for IRQ 1

intr

Interrupt Status (raw)

ints0

Interrupt Status for IRQ 0

ints1

Interrupt Status (masked) for IRQ 1

multi_chan_trigger

Trigger one or more channels simultaneously

n_channels

The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

sniff_ctrl

Sniffer Control

sniff_data

Data accumulator for sniff hardware\n Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.

timer0

Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

timer1

Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

Structs

RegisterBlock

Register block

Type Definitions

CH0_AL1_CTRL

Alias for channel 0 CTRL register

CH0_AL1_READ_ADDR

Alias for channel 0 READ_ADDR register

CH0_AL1_TRANS_COUNT_TRIG

Alias for channel 0 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH0_AL1_WRITE_ADDR

Alias for channel 0 WRITE_ADDR register

CH0_AL2_CTRL

Alias for channel 0 CTRL register

CH0_AL2_READ_ADDR

Alias for channel 0 READ_ADDR register

CH0_AL2_TRANS_COUNT

Alias for channel 0 TRANS_COUNT register

CH0_AL2_WRITE_ADDR_TRIG

Alias for channel 0 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH0_AL3_CTRL

Alias for channel 0 CTRL register

CH0_AL3_READ_ADDR_TRIG

Alias for channel 0 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH0_AL3_TRANS_COUNT

Alias for channel 0 TRANS_COUNT register

CH0_AL3_WRITE_ADDR

Alias for channel 0 WRITE_ADDR register

CH0_CTRL_TRIG

DMA Channel 0 Control and Status

CH0_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH0_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH0_READ_ADDR

DMA Channel 0 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH0_TRANS_COUNT

DMA Channel 0 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH0_WRITE_ADDR

DMA Channel 0 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH1_AL1_CTRL

Alias for channel 1 CTRL register

CH1_AL1_READ_ADDR

Alias for channel 1 READ_ADDR register

CH1_AL1_TRANS_COUNT_TRIG

Alias for channel 1 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH1_AL1_WRITE_ADDR

Alias for channel 1 WRITE_ADDR register

CH1_AL2_CTRL

Alias for channel 1 CTRL register

CH1_AL2_READ_ADDR

Alias for channel 1 READ_ADDR register

CH1_AL2_TRANS_COUNT

Alias for channel 1 TRANS_COUNT register

CH1_AL2_WRITE_ADDR_TRIG

Alias for channel 1 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH1_AL3_CTRL

Alias for channel 1 CTRL register

CH1_AL3_READ_ADDR_TRIG

Alias for channel 1 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH1_AL3_TRANS_COUNT

Alias for channel 1 TRANS_COUNT register

CH1_AL3_WRITE_ADDR

Alias for channel 1 WRITE_ADDR register

CH1_CTRL_TRIG

DMA Channel 1 Control and Status

CH1_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH1_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH1_READ_ADDR

DMA Channel 1 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH1_TRANS_COUNT

DMA Channel 1 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH1_WRITE_ADDR

DMA Channel 1 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH2_AL1_CTRL

Alias for channel 2 CTRL register

CH2_AL1_READ_ADDR

Alias for channel 2 READ_ADDR register

CH2_AL1_TRANS_COUNT_TRIG

Alias for channel 2 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH2_AL1_WRITE_ADDR

Alias for channel 2 WRITE_ADDR register

CH2_AL2_CTRL

Alias for channel 2 CTRL register

CH2_AL2_READ_ADDR

Alias for channel 2 READ_ADDR register

CH2_AL2_TRANS_COUNT

Alias for channel 2 TRANS_COUNT register

CH2_AL2_WRITE_ADDR_TRIG

Alias for channel 2 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH2_AL3_CTRL

Alias for channel 2 CTRL register

CH2_AL3_READ_ADDR_TRIG

Alias for channel 2 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH2_AL3_TRANS_COUNT

Alias for channel 2 TRANS_COUNT register

CH2_AL3_WRITE_ADDR

Alias for channel 2 WRITE_ADDR register

CH2_CTRL_TRIG

DMA Channel 2 Control and Status

CH2_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH2_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH2_READ_ADDR

DMA Channel 2 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH2_TRANS_COUNT

DMA Channel 2 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH2_WRITE_ADDR

DMA Channel 2 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH3_AL1_CTRL

Alias for channel 3 CTRL register

CH3_AL1_READ_ADDR

Alias for channel 3 READ_ADDR register

CH3_AL1_TRANS_COUNT_TRIG

Alias for channel 3 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH3_AL1_WRITE_ADDR

Alias for channel 3 WRITE_ADDR register

CH3_AL2_CTRL

Alias for channel 3 CTRL register

CH3_AL2_READ_ADDR

Alias for channel 3 READ_ADDR register

CH3_AL2_TRANS_COUNT

Alias for channel 3 TRANS_COUNT register

CH3_AL2_WRITE_ADDR_TRIG

Alias for channel 3 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH3_AL3_CTRL

Alias for channel 3 CTRL register

CH3_AL3_READ_ADDR_TRIG

Alias for channel 3 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH3_AL3_TRANS_COUNT

Alias for channel 3 TRANS_COUNT register

CH3_AL3_WRITE_ADDR

Alias for channel 3 WRITE_ADDR register

CH3_CTRL_TRIG

DMA Channel 3 Control and Status

CH3_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH3_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH3_READ_ADDR

DMA Channel 3 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH3_TRANS_COUNT

DMA Channel 3 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH3_WRITE_ADDR

DMA Channel 3 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH4_AL1_CTRL

Alias for channel 4 CTRL register

CH4_AL1_READ_ADDR

Alias for channel 4 READ_ADDR register

CH4_AL1_TRANS_COUNT_TRIG

Alias for channel 4 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH4_AL1_WRITE_ADDR

Alias for channel 4 WRITE_ADDR register

CH4_AL2_CTRL

Alias for channel 4 CTRL register

CH4_AL2_READ_ADDR

Alias for channel 4 READ_ADDR register

CH4_AL2_TRANS_COUNT

Alias for channel 4 TRANS_COUNT register

CH4_AL2_WRITE_ADDR_TRIG

Alias for channel 4 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH4_AL3_CTRL

Alias for channel 4 CTRL register

CH4_AL3_READ_ADDR_TRIG

Alias for channel 4 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH4_AL3_TRANS_COUNT

Alias for channel 4 TRANS_COUNT register

CH4_AL3_WRITE_ADDR

Alias for channel 4 WRITE_ADDR register

CH4_CTRL_TRIG

DMA Channel 4 Control and Status

CH4_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH4_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH4_READ_ADDR

DMA Channel 4 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH4_TRANS_COUNT

DMA Channel 4 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH4_WRITE_ADDR

DMA Channel 4 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH5_AL1_CTRL

Alias for channel 5 CTRL register

CH5_AL1_READ_ADDR

Alias for channel 5 READ_ADDR register

CH5_AL1_TRANS_COUNT_TRIG

Alias for channel 5 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH5_AL1_WRITE_ADDR

Alias for channel 5 WRITE_ADDR register

CH5_AL2_CTRL

Alias for channel 5 CTRL register

CH5_AL2_READ_ADDR

Alias for channel 5 READ_ADDR register

CH5_AL2_TRANS_COUNT

Alias for channel 5 TRANS_COUNT register

CH5_AL2_WRITE_ADDR_TRIG

Alias for channel 5 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH5_AL3_CTRL

Alias for channel 5 CTRL register

CH5_AL3_READ_ADDR_TRIG

Alias for channel 5 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH5_AL3_TRANS_COUNT

Alias for channel 5 TRANS_COUNT register

CH5_AL3_WRITE_ADDR

Alias for channel 5 WRITE_ADDR register

CH5_CTRL_TRIG

DMA Channel 5 Control and Status

CH5_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH5_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH5_READ_ADDR

DMA Channel 5 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH5_TRANS_COUNT

DMA Channel 5 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH5_WRITE_ADDR

DMA Channel 5 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH6_AL1_CTRL

Alias for channel 6 CTRL register

CH6_AL1_READ_ADDR

Alias for channel 6 READ_ADDR register

CH6_AL1_TRANS_COUNT_TRIG

Alias for channel 6 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH6_AL1_WRITE_ADDR

Alias for channel 6 WRITE_ADDR register

CH6_AL2_CTRL

Alias for channel 6 CTRL register

CH6_AL2_READ_ADDR

Alias for channel 6 READ_ADDR register

CH6_AL2_TRANS_COUNT

Alias for channel 6 TRANS_COUNT register

CH6_AL2_WRITE_ADDR_TRIG

Alias for channel 6 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH6_AL3_CTRL

Alias for channel 6 CTRL register

CH6_AL3_READ_ADDR_TRIG

Alias for channel 6 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH6_AL3_TRANS_COUNT

Alias for channel 6 TRANS_COUNT register

CH6_AL3_WRITE_ADDR

Alias for channel 6 WRITE_ADDR register

CH6_CTRL_TRIG

DMA Channel 6 Control and Status

CH6_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH6_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH6_READ_ADDR

DMA Channel 6 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH6_TRANS_COUNT

DMA Channel 6 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH6_WRITE_ADDR

DMA Channel 6 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH7_AL1_CTRL

Alias for channel 7 CTRL register

CH7_AL1_READ_ADDR

Alias for channel 7 READ_ADDR register

CH7_AL1_TRANS_COUNT_TRIG

Alias for channel 7 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH7_AL1_WRITE_ADDR

Alias for channel 7 WRITE_ADDR register

CH7_AL2_CTRL

Alias for channel 7 CTRL register

CH7_AL2_READ_ADDR

Alias for channel 7 READ_ADDR register

CH7_AL2_TRANS_COUNT

Alias for channel 7 TRANS_COUNT register

CH7_AL2_WRITE_ADDR_TRIG

Alias for channel 7 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH7_AL3_CTRL

Alias for channel 7 CTRL register

CH7_AL3_READ_ADDR_TRIG

Alias for channel 7 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH7_AL3_TRANS_COUNT

Alias for channel 7 TRANS_COUNT register

CH7_AL3_WRITE_ADDR

Alias for channel 7 WRITE_ADDR register

CH7_CTRL_TRIG

DMA Channel 7 Control and Status

CH7_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH7_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH7_READ_ADDR

DMA Channel 7 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH7_TRANS_COUNT

DMA Channel 7 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH7_WRITE_ADDR

DMA Channel 7 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH8_AL1_CTRL

Alias for channel 8 CTRL register

CH8_AL1_READ_ADDR

Alias for channel 8 READ_ADDR register

CH8_AL1_TRANS_COUNT_TRIG

Alias for channel 8 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH8_AL1_WRITE_ADDR

Alias for channel 8 WRITE_ADDR register

CH8_AL2_CTRL

Alias for channel 8 CTRL register

CH8_AL2_READ_ADDR

Alias for channel 8 READ_ADDR register

CH8_AL2_TRANS_COUNT

Alias for channel 8 TRANS_COUNT register

CH8_AL2_WRITE_ADDR_TRIG

Alias for channel 8 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH8_AL3_CTRL

Alias for channel 8 CTRL register

CH8_AL3_READ_ADDR_TRIG

Alias for channel 8 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH8_AL3_TRANS_COUNT

Alias for channel 8 TRANS_COUNT register

CH8_AL3_WRITE_ADDR

Alias for channel 8 WRITE_ADDR register

CH8_CTRL_TRIG

DMA Channel 8 Control and Status

CH8_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH8_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH8_READ_ADDR

DMA Channel 8 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH8_TRANS_COUNT

DMA Channel 8 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH8_WRITE_ADDR

DMA Channel 8 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH9_AL1_CTRL

Alias for channel 9 CTRL register

CH9_AL1_READ_ADDR

Alias for channel 9 READ_ADDR register

CH9_AL1_TRANS_COUNT_TRIG

Alias for channel 9 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH9_AL1_WRITE_ADDR

Alias for channel 9 WRITE_ADDR register

CH9_AL2_CTRL

Alias for channel 9 CTRL register

CH9_AL2_READ_ADDR

Alias for channel 9 READ_ADDR register

CH9_AL2_TRANS_COUNT

Alias for channel 9 TRANS_COUNT register

CH9_AL2_WRITE_ADDR_TRIG

Alias for channel 9 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH9_AL3_CTRL

Alias for channel 9 CTRL register

CH9_AL3_READ_ADDR_TRIG

Alias for channel 9 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH9_AL3_TRANS_COUNT

Alias for channel 9 TRANS_COUNT register

CH9_AL3_WRITE_ADDR

Alias for channel 9 WRITE_ADDR register

CH9_CTRL_TRIG

DMA Channel 9 Control and Status

CH9_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH9_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH9_READ_ADDR

DMA Channel 9 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH9_TRANS_COUNT

DMA Channel 9 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH9_WRITE_ADDR

DMA Channel 9 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH10_AL1_CTRL

Alias for channel 10 CTRL register

CH10_AL1_READ_ADDR

Alias for channel 10 READ_ADDR register

CH10_AL1_TRANS_COUNT_TRIG

Alias for channel 10 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH10_AL1_WRITE_ADDR

Alias for channel 10 WRITE_ADDR register

CH10_AL2_CTRL

Alias for channel 10 CTRL register

CH10_AL2_READ_ADDR

Alias for channel 10 READ_ADDR register

CH10_AL2_TRANS_COUNT

Alias for channel 10 TRANS_COUNT register

CH10_AL2_WRITE_ADDR_TRIG

Alias for channel 10 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH10_AL3_CTRL

Alias for channel 10 CTRL register

CH10_AL3_READ_ADDR_TRIG

Alias for channel 10 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH10_AL3_TRANS_COUNT

Alias for channel 10 TRANS_COUNT register

CH10_AL3_WRITE_ADDR

Alias for channel 10 WRITE_ADDR register

CH10_CTRL_TRIG

DMA Channel 10 Control and Status

CH10_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH10_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH10_READ_ADDR

DMA Channel 10 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH10_TRANS_COUNT

DMA Channel 10 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH10_WRITE_ADDR

DMA Channel 10 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CH11_AL1_CTRL

Alias for channel 11 CTRL register

CH11_AL1_READ_ADDR

Alias for channel 11 READ_ADDR register

CH11_AL1_TRANS_COUNT_TRIG

Alias for channel 11 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH11_AL1_WRITE_ADDR

Alias for channel 11 WRITE_ADDR register

CH11_AL2_CTRL

Alias for channel 11 CTRL register

CH11_AL2_READ_ADDR

Alias for channel 11 READ_ADDR register

CH11_AL2_TRANS_COUNT

Alias for channel 11 TRANS_COUNT register

CH11_AL2_WRITE_ADDR_TRIG

Alias for channel 11 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH11_AL3_CTRL

Alias for channel 11 CTRL register

CH11_AL3_READ_ADDR_TRIG

Alias for channel 11 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.

CH11_AL3_TRANS_COUNT

Alias for channel 11 TRANS_COUNT register

CH11_AL3_WRITE_ADDR

Alias for channel 11 WRITE_ADDR register

CH11_CTRL_TRIG

DMA Channel 11 Control and Status

CH11_DBG_CTDREQ

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

CH11_DBG_TCR

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

CH11_READ_ADDR

DMA Channel 11 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

CH11_TRANS_COUNT

DMA Channel 11 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

CH11_WRITE_ADDR

DMA Channel 11 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

CHAN_ABORT

Abort an in-progress transfer sequence on one or more channels

FIFO_LEVELS

Debug RAF, WAF, TDF levels

INTE0

Interrupt Enables for IRQ 0

INTE1

Interrupt Enables for IRQ 1

INTF0

Force Interrupts

INTF1

Force Interrupts for IRQ 1

INTR

Interrupt Status (raw)

INTS0

Interrupt Status for IRQ 0

INTS1

Interrupt Status (masked) for IRQ 1

MULTI_CHAN_TRIGGER

Trigger one or more channels simultaneously

N_CHANNELS

The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

SNIFF_CTRL

Sniffer Control

SNIFF_DATA

Data accumulator for sniff hardware\n Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.

TIMER0

Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

TIMER1

Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.