Type Definition rp2040::dma::ch8_ctrl_trig::W

type W = W<u32, CH8_CTRL_TRIG>;

Writer for register CH8_CTRL_TRIG

Implementations

impl W

pub fn read_error(&mut self) -> READ_ERROR_W<'_>

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

pub fn write_error(&mut self) -> WRITE_ERROR_W<'_>

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

pub fn sniff_en(&mut self) -> SNIFF_EN_W<'_>

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

pub fn bswap(&mut self) -> BSWAP_W<'_>

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<'_>

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

pub fn treq_sel(&mut self) -> TREQ_SEL_W<'_>

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

pub fn chain_to(&mut self) -> CHAIN_TO_W<'_>

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (8).

pub fn ring_sel(&mut self) -> RING_SEL_W<'_>

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

pub fn ring_size(&mut self) -> RING_SIZE_W<'_>

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

pub fn incr_write(&mut self) -> INCR_WRITE_W<'_>

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

pub fn incr_read(&mut self) -> INCR_READ_W<'_>

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

pub fn data_size(&mut self) -> DATA_SIZE_W<'_>

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<'_>

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)