Type Alias rp2040_pac::sio::interp1_ctrl_lane0::R
source · pub type R = R<INTERP1_CTRL_LANE0_SPEC>;
Expand description
Register INTERP1_CTRL_LANE0
reader
Aliased Type§
struct R { /* private fields */ }
Implementations§
source§impl R
impl R
sourcepub fn shift(&self) -> SHIFT_R
pub fn shift(&self) -> SHIFT_R
Bits 0:4 - Logical right-shift applied to accumulator before masking
sourcepub fn mask_lsb(&self) -> MASK_LSB_R
pub fn mask_lsb(&self) -> MASK_LSB_R
Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)
sourcepub fn mask_msb(&self) -> MASK_MSB_R
pub fn mask_msb(&self) -> MASK_MSB_R
Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)
Setting MSB < LSB may cause chip to turn inside-out
sourcepub fn signed(&self) -> SIGNED_R
pub fn signed(&self) -> SIGNED_R
Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
sourcepub fn cross_input(&self) -> CROSS_INPUT_R
pub fn cross_input(&self) -> CROSS_INPUT_R
Bit 16 - If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.
Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
sourcepub fn cross_result(&self) -> CROSS_RESULT_R
pub fn cross_result(&self) -> CROSS_RESULT_R
Bit 17 - If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
sourcepub fn add_raw(&self) -> ADD_RAW_R
pub fn add_raw(&self) -> ADD_RAW_R
Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
sourcepub fn force_msb(&self) -> FORCE_MSB_R
pub fn force_msb(&self) -> FORCE_MSB_R
Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.
No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
of pointers into flash or SRAM.