Struct rp2040_hal::pwm::SliceDmaWriteCc

pub struct SliceDmaWriteCc<S: SliceId, M: ValidSliceMode<S>> { /* private fields */ }

Type representing DMA access to PWM cc register.

Both channels are accessed together, because of narrow write replication.

use cortex_m::singleton;
use rp2040_hal::dma::{double_buffer, DMAExt};
use rp2040_hal::pwm::{CcFormat, SliceDmaWrite, Slices};


let mut pac = rp2040_pac::Peripherals::take().unwrap();

// Init PWMs
let pwm_slices = Slices::new(pac.PWM, &mut pac.RESETS);

// Configure PWM4
let mut pwm = pwm_slices.pwm4;
pwm.enable();

let buf = singleton!(: [CcFormat; 4] = [CcFormat{a: 0x1000, b: 0x9000}; 4]).unwrap();
let buf2 = singleton!(: [CcFormat; 4] = [CcFormat{a: 0xf000, b: 0x5000}; 4]).unwrap();

let dma = pac.DMA.split(&mut pac.RESETS);

let dma_pwm = SliceDmaWrite::from(pwm);

let dma_conf = double_buffer::Config::new((dma.ch0, dma.ch1), buf, dma_pwm.cc);

Trait Implementations

impl<S: SliceId, M: ValidSliceMode<S>> WriteTarget for SliceDmaWriteCc<S, M>

Safety: tx_address_count points to a register which is always a valid write target.

type TransmittedWord = CcFormat

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<S: SliceId, M: ValidSliceMode<S>> EndlessWriteTarget for SliceDmaWriteCc<S, M>