Struct rp2040_hal::pwm::Slice

pub struct Slice<I, M>
where
    I: SliceId,
    M: ValidSliceMode<I>,
{
    pub channel_a: Channel<Self, A>,
    pub channel_b: Channel<Self, B>,
    /* private fields */
}

Pwm slice

Fields

channel_a: Channel<Self, A>

Channel A (always output)

channel_b: Channel<Self, B>

Channel B (input or output)

Implementations

impl<I, M> Slice<I, M>

where I: SliceId, M: ValidSliceMode<I>,

pub fn into_mode<N: ValidSliceMode<I>>(self) -> Slice<I, N>

Convert the slice to the requested SliceMode

pub fn default_config(&mut self)

Set a default config for the slice

pub fn advance_phase(&mut self)

Advance the phase with one count

Counter must be running at less than full speed (div_int + div_frac / 16 > 1)

pub fn retard_phase(&mut self)

Retard the phase with one count

Counter must be running at less than full speed (div_int + div_frac / 16 > 1)

pub fn set_ph_correct(&mut self)

Enable phase correct mode

pub fn clr_ph_correct(&mut self)

Disables phase correct mode

pub fn enable(&mut self)

Enable slice

pub fn disable(&mut self)

Disable slice

pub fn set_div_int(&mut self, value: u8)

Sets the integer part of the clock divider

pub fn set_div_frac(&mut self, value: u8)

Sets the fractional part of the clock divider

pub fn get_counter(&self) -> u16

Get the counter register value

pub fn set_counter(&mut self, value: u16)

Set the counter register value

pub fn get_top(&self) -> u16

Get the top register value

pub fn set_top(&mut self, value: u16)

Sets the top register value

Don’t set this to 0xffff if you need true 100% duty cycle:

The CC register, which is used to configure the duty cycle, must be set to TOP + 1 for 100% duty cycle, but also is a 16 bit register.

In case you do set TOP to 0xffff, SetDutyCycle::set_duty_cycle will slightly violate the trait’s documentation, as SetDutyCycle::set_duty_cycle_fully_on and other calls that should lead to 100% duty cycle will only reach a duty cycle of about 99.998%.

pub fn enable_interrupt(&mut self)

Enable the PWM_IRQ_WRAP interrupt when this slice overflows.

pub fn disable_interrupt(&mut self)

Disable the PWM_IRQ_WRAP interrupt for this slice.

pub fn has_overflown(&self) -> bool

Did this slice trigger an overflow interrupt?

This reports the raw interrupt flag, without considering masking or forcing bits. It may return true even if the interrupt is disabled or false even if the interrupt is forced.

pub fn clear_interrupt(&mut self)

Mark the interrupt handled for this slice.

pub fn force_interrupt(&mut self)

Force the interrupt. This bit is not cleared by hardware and must be manually cleared to stop the interrupt from continuing to be asserted.

pub fn clear_force_interrupt(&mut self)

Clear force interrupt. This bit is not cleared by hardware and must be manually cleared to stop the interrupt from continuing to be asserted.

impl<S: SliceId, M: ValidSliceMode<S>> Slice<S, M>

pub fn output_to<P: AnyPin, C: ChannelId>( &mut self, pin: P ) -> Pin<P::Id, FunctionPwm, P::Pull>

where P::Id: ValidPwmOutputPin<S, C>,

Capture a gpio pin and use it as pwm output

impl<S: SliceId, M: ValidSliceInputMode<S>> Slice<S, M>

pub fn input_from<P: AnyPin>( &mut self, pin: P ) -> Pin<P::Id, FunctionPwm, P::Pull>

where P::Id: ValidPwmInputPin<S>,

Capture a gpio pin and use it as pwm input for channel B

Trait Implementations

impl<S, M> AnySlice for Slice<S, M>

where S: SliceId, M: ValidSliceMode<S>,

type Id = S

SliceId of the corresponding Slice

type Mode = M

SliceMode of the corresponding Slice

impl<S: SliceId, M: ValidSliceMode<S>> From<Slice<S, M>> for SliceDmaWrite<S, M>

fn from(value: Slice<S, M>) -> Self

Converts to this type from the input type.

impl<S: SliceId, M: ValidSliceMode<S>> From<SliceDmaWrite<S, M>> for Slice<S, M>

fn from(value: SliceDmaWrite<S, M>) -> Self

Converts to this type from the input type.