Struct HwModel 

pub struct HwModel {
    pub neon_flops: f64,
    pub blas_flops: f64,
    pub blas_overhead_ns: f64,
    pub par_for_overhead_ns: f64,
    pub l1_bytes: usize,
    pub l2_bytes: usize,
    pub mem_bw: f64,
    pub num_threads: usize,
}

Hardware model — derived from RuntimeConfig + platform detection.

Fields

neon_flops: f64

NEON throughput: FLOP/s for element-wise (FMA chains)

blas_flops: f64

BLAS throughput: FLOP/s for sgemm (AMX or optimized NEON)

blas_overhead_ns: f64

BLAS call overhead in nanoseconds (function call + AMX sync)

par_for_overhead_ns: f64

par_for dispatch overhead in nanoseconds

l1_bytes: usize

L1 data cache size in bytes

l2_bytes: usize

L2 cache size in bytes

mem_bw: f64

Memory bandwidth (L2 → registers) in bytes/ns

num_threads: usize

Number of worker threads

Implementations

impl HwModel

pub fn from_config(cfg: &RuntimeConfig) -> Self

Build from runtime config and platform defaults.

pub fn prefer_neon_sgemm(&self, m: usize, k: usize, n: usize) -> bool

Should we use NEON sgemm instead of BLAS for this matrix multiply? Returns true when BLAS overhead dominates the compute.

pub fn prefer_parallel( &self, total_elements: usize, cost_per_element_ns: f64, ) -> bool

Should we use par_for for this element-wise operation? Returns true when parallelism benefit exceeds dispatch overhead.

pub fn prefer_blas_sdpa( &self, batch: usize, seq: usize, num_heads: usize, head_dim: usize, ) -> bool

Should we use strided BLAS for SDPA, or sequential NEON dots?

pub fn prefer_fused_layer( &self, batch: usize, seq: usize, hidden: usize, intermediate: usize, ) -> bool

Should we fuse the entire transformer layer into one thunk? True when intermediates fit in L1 and per-thunk overhead dominates.