Struct DeviceWrite 

pub struct DeviceWrite<'a, T: Copy, const N: usize> { /* private fields */ }

One-shot DMA-write typestate handle.

While alive, the CPU MUST NOT access the buffer. Drop or DeviceWrite::complete returns the buffer to Cpu state with no exit cache op (the entry-side invalidate already prepared the cache for the post-transfer CPU read).

Implementations

impl<'a, T: Copy, const N: usize> DeviceWrite<'a, T, N>

pub fn dma_addr(&self) -> DmaAddr

DMA bus address of the buffer.

pub fn complete(self) -> Cpu<'a, T, N>

Transition back to Cpu state.

Per DCB-00 §5 transition table: no cache op at exit. The entry-side invalidate evicted the buffer’s cache lines, INV-D3 forbids adjacent-line refill from reintroducing stale data during transfer, so the CPU’s first read after this call hits RAM and observes the DMA-written data.