Struct LtdcScan 

pub struct LtdcScan<'a, T: Copy, const N: usize> { /* private fields */ }

Continuous-read typestate handle for fixed-rate pixel-stream consumers (LTDC, DCMI display-out, parallel RGB).

Distinguished from CircRead:

• the consumer never pauses (no half-rotation; same buffer is read continuously),
• the CPU paints in place between consumer reads rather than producing into an inactive half,
• per-frame ordering is enforced by LtdcScan::present (clean plus DSB) at checkpoints chosen by the caller, not by an engine-side completion flag.

The DIR parameter is deliberately omitted — the CPU is always producer for this family. The inverse direction (camera frame-grab via DCMI) would be a separate LtdcGrab family; not in scope here, would ratify in a future §15 amendment with a named first user.

Implementations

impl<'a, T: Copy, const N: usize> LtdcScan<'a, T, N>

pub fn dma_addr(&self) -> DmaAddr

DMA bus address of the buffer (stable for the typestate’s lifetime; equal to the address returned during the start_ltdc_scan transition). Pass to the consumer engine’s frame-buffer base register (e.g. LTDC CFBAR).

pub fn paint_full(&mut self) -> &mut [T; N]

In-place CPU access to the full buffer.

Returns a &mut [T; N] valid until the next call that borrows self mutably (LtdcScan::present / LtdcScan::stop_scan). The borrow checker rejects concurrent paint_full / present calls.

No cache op is emitted here; ordering between the CPU’s writes and the consumer’s reads is enforced at present (DCB-00 §5 transition table).

pub fn present<C: DcaCache>(&mut self, ctx: &mut DcaCacheCtx<'_, C>)

Per-frame checkpoint: publish CPU writes to RAM for the consumer’s next read.

Per DCB-00 §6 INV-D16 emits both DcaCache::clean over the full padded extent AND DcaCache::barrier (DSB-equivalent). Does not transition the typestate — the consumer engine is still reading; only the ordering between CPU writes and consumer reads is checkpointed.

pub fn stop_scan<C: DcaCache>( self, ctx: &mut DcaCacheCtx<'_, C>, ) -> Cpu<'a, T, N>

Transition back to Cpu.

Caller MUST stop the consumer engine before calling. Per DCB-00 §5: emits a final DcaCache::clean + DcaCache::barrier over the full padded extent so the next phase’s CPU read sees the buffer’s terminal state.