Struct rk3399_rs::Hdmi

pub struct Hdmi { /* private fields */ }

HDMI

Implementations

impl Hdmi

pub const PTR: *const RegisterBlock = {0xff940000 as *const hdmi::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn design_id(&self) -> &DesignId

0x00 - Design ID code fixed by HDMI that Identifies the instantiated DWC_hdmi_tx controller. For example, DWC_hdmi_tx 2.11a, DESIGN_ID = 21

pub fn revision_id(&self) -> &RevisionId

0x01 - Revision ID code fixed by HDMI that Identifies the instantiated DWC_hdmi_tx controller.

pub fn product_id0(&self) -> &ProductId0

0x02 - This one byte fixed code Identifies HDMI ’s product line (“A0h” for DWC_hdmi_tx products).

pub fn product_id1(&self) -> &ProductId1

0x03 - This bit Identifies H Controller according to HDMI product line.

pub fn config0_id(&self) -> &Config0Id

0x04 - Indicates if HDCP is present

pub fn config1_id(&self) -> &Config1Id

0x05 - Reserved for future use.

pub fn config2_id(&self) -> &Config2Id

0x06 - Indicates the type of PHY interface selected: 0x00: Legacy PHY (HDMI Tx PHY) 0xF2: PHY GEN2 (HDMI 3D TX PHY) 0xE2: PHY GEN2 (HDMI 3D TX PHY) + HEAC PHY 0xC2: PHY MHL COMBO (MHL+HDMI 2.0 TX PHY) 0xB2: PHY MHL COMBO (MHL+HDMI 2.0 TX PHY) + HEAC PHY 0xF3: PHY HDMI 20 (HDMI 2.0 TX PHY) 0xE3: PHY HDMI 20 (HDMI 2.0 TX PHY) + HEAC PHY 0xFE: External PHY

pub fn config3_id(&self) -> &Config3Id

0x07 - Indicates that the audio interface is Generic Parallel Audio (GPAUD)

pub fn ih_fc_stat0(&self) -> &IhFcStat0

0x100 - Active after successful transmission of an Null packet. Due to high number of audio sample packets transmitted, this interrupt is by default masked at frame composer.

pub fn ih_fc_stat1(&self) -> &IhFcStat1

0x101 - Active after successful transmission of an General Control Packet.

pub fn ih_fc_stat2(&self) -> &IhFcStat2

0x102 - Frame Composer high priority packet queue descriptor overflow indication

pub fn ih_as_stat0(&self) -> &IhAsStat0

0x103 - Audio Sampler audio FIFO full indication.

pub fn ih_phy_stat0(&self) -> &IhPhyStat0

0x104 - HDMI Hot Plug Detect indication. You may need to mask or change polarity of this interrupt after it has become active.

pub fn ih_i2cm_stat0(&self) -> &IhI2cmStat0

0x105 - I2C Master error indication

pub fn ih_cec_stat0(&self) -> &IhCecStat0

0x106 - CEC Done Indication

pub fn ih_vp_stat0(&self) -> &IhVpStat0

0x107 - Reserved and read as zero

pub fn ih_i2cmphy_stat0(&self) -> &IhI2cmphyStat0

0x108 - I2C Master PHY error indication

pub fn ih_ahbdmaaud_stat0(&self) -> &IhAhbdmaaudStat0

0x109 - AHB audio DMA lost ownership interrupt

pub fn ih_decode(&self) -> &IhDecode

0x170 - Interruption active at the ih_ahbdmaaud_stat0 register

pub fn ih_mute_fc_stat0(&self) -> &IhMuteFcStat0

0x180 - When set to 1, mutes ih_fc_stat0[0]

pub fn ih_mute_fc_stat1(&self) -> &IhMuteFcStat1

0x181 - When set to 1, mutes ih_fc_stat1[2]. Otherwise, this field is a “spare” bit with no associated functionality.

pub fn ih_mute_fc_stat2(&self) -> &IhMuteFcStat2

0x182 - When set to 1, mutes ih_fc_stat2[0]

pub fn ih_mute_as_stat0(&self) -> &IhMuteAsStat0

0x183 - When set to 1, mutes ih_as_stat0[0]

pub fn ih_mute_phy_stat0(&self) -> &IhMutePhyStat0

0x184 - When set to 1, mutes ih_phy_stat0[0]

pub fn ih_mute_i2cm_stat0(&self) -> &IhMuteI2cmStat0

0x185 - When set to 1, mutes ih_i2cm_stat0[0]

pub fn ih_mute_cec_stat0(&self) -> &IhMuteCecStat0

0x186 - When set to 1, mutes ih_cec_stat0[0]

pub fn ih_mute_vp_stat0(&self) -> &IhMuteVpStat0

0x187 - Reserved as “spare” bit with no associated functionality.

pub fn ih_mute_i2cmphy_stat0(&self) -> &IhMuteI2cmphyStat0

0x188 - When set to 1, mutes ih_i2cmphy_stat0[0]

pub fn ih_mute_ahbdmaaud_stat0(&self) -> &IhMuteAhbdmaaudStat0

0x189 - When set to 1, mutes ih_ahbdmaaud_stat0[0]

pub fn ih_mute(&self) -> &IhMute

0x1ff - When set to 1, mutes the main interrupt line (where all interrupts are ORed). The sticky bit interrupts continue with their state; only the main interrupt line is muted.

pub fn tx_invid0(&self) -> &TxInvid0

0x200 - Internal data enable (DE) generator enable. If data enable is not available for the input video, set this bit to one to activate the internal data enable generator. Attention: This feature only works for input video modes that have native repetition (such as, all CEA videos). No desired pixel repetition can be used with this feature because these configurations only affect the Frame Composer and not this block. The DE Generator does not work for the following conditions: Transmission of video with CEA VIC 39 Transmission of 3D video using the field alternative structure

pub fn tx_instuffing(&self) -> &TxInstuffing

0x201 - 0b: When the dataen signal is low, the value in the gydata[15:0] output is the one sampled from the corresponding input data. 1b: When the dataen signal is low, the value in the gydata[15:0] output is given by the values in TX_GYDTA0 and TX_GYDATA1 registers.

pub fn tx_gydata0(&self) -> &TxGydata0

0x202 - This register defines the value of gydata[7:0] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b.

pub fn tx_gydata1(&self) -> &TxGydata1

0x203 - This register defines the value of gydata[15:8] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b.

pub fn tx_rcrdata0(&self) -> &TxRcrdata0

0x204 - This register defines the value of rcrydata[7:0] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b.

pub fn tx_rcrdata1(&self) -> &TxRcrdata1

0x205 - This register defines the value of rcrydata[15:8] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b.

pub fn tx_bcbdata0(&self) -> &TxBcbdata0

0x206 - This register defines the value of bcbdata[7:0] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b.

pub fn tx_bcbdata1(&self) -> &TxBcbdata1

0x207 - This register defines the value of bcbdata[15:8] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b.

pub fn vp_status(&self) -> &VpStatus

0x800 - Read only register that holds the “packing phase” output of the Video Packetizer block.

pub fn vp_pr_cd(&self) -> &VpPrCd

0x801 - Desired pixel repetition factor configuration. The configured value sets H13T PHY PLL to multiply pixel clock by the factor in order to obtain the desired repetition clock. For the CEA modes some are already defined with pixel repetition in the input video. So for CEA modes this shall be always 0. Shall only be used if the user wants to do pixel repetition using H13TCTRL controller. The action is stated corresponding to desired_pr_factor[3:0]: 0000b: No pixel repetition (pixel sent only once) 0001b: Pixel sent two times (pixel repeated once) 0010b: Pixel sent three times 0011b: Pixel sent four times 0100b: Pixel sent five times 0101b: Pixel sent six times 0110b: Pixel sent seven times 0111b: Pixel sent eight times 1000b: Pixel sent nine times 1001b: Pixel sent 10 times Other: Reserved. Not used

pub fn vp_stuff(&self) -> &VpStuff

0x802 - Pixel packing stuffing control. The action is stated corresponding to pp_stuffing: 0b: Pixel packing block in direct mode (input blanking data goes directly to output). 1b: Pixel packing block in stuffing mode. When “de_rep” goes to low the outputs are fixed to 0x00.

pub fn vp_remap(&self) -> &VpRemap

0x803 - YCC 422 remap input video size ycc422_size[1:0] 00b: YCC 422 16-bit input video (8 bits per component) 01b: YCC 422 20-bit input video (10 bits per component) 10b: YCC 422 24-bit input video (12 bits per component) 11b: Reserved. Not used

pub fn vp_conf(&self) -> &VpConf

0x804 - Video Packetizer output selection 0b: Data from pixel packing block 1b: Data from YCC422 remap block

pub fn vp_mask(&self) -> &VpMask

0x807 - Reserved as “spare” bit with no associated functionality.

pub fn fc_invidconf(&self) -> &FcInvidconf

0x1000 - Used for CEA861-D modes with fractional Vblank (for example, modes 5, 6, 7, 10, 11, 20, 21, and 22). For more modes, see the CEA861-D specification. Note: Set this field to 1 for video mode 39, although there is no Vblank oscillation. 1b: Active high

pub fn fc_inhactiv0(&self) -> &FcInhactiv0

0x1001 - Input video Horizontal active pixel region width. Number of Horizontal active pixels [0…8191].

pub fn fc_inhactiv1(&self) -> &FcInhactiv1

0x1002 - Input video Horizontal active pixel region width (0 .. 16383) If the configuration parameter HDMI_TX_20 = True (1), this bit field holds bit 13.

pub fn fc_inhblank0(&self) -> &FcInhblank0

0x1003 - Input video Horizontal blanking pixel region width. Number of Horizontal blanking pixels [0…4095].

pub fn fc_inhblank1(&self) -> &FcInhblank1

0x1004 - Input video Horizontal blanking pixel region width this bit field holds bits 9:8 of number of Horizontal blanking pixels.

pub fn fc_invactiv0(&self) -> &FcInvactiv0

0x1005 - Input video Vertical active pixel region width. This bit field holds bits 7:0 of number of Vertical active pixels.

pub fn fc_invactiv1(&self) -> &FcInvactiv1

0x1006 - Input video Vertical active pixel region width. This bit field holds bits 9:8 of number of Vertical active pixels.

pub fn fc_invblank(&self) -> &FcInvblank

0x1007 - Input video Vertical blanking pixel region width. Number of Vertical blanking lines [0…255].

pub fn fc_hsyncindelay0(&self) -> &FcHsyncindelay0

0x1008 - Input video Hsync active edge delay. Integer number of pixel clock cycles from “de” non active edge of the last “de” valid period [0…4095].

pub fn fc_hsyncindelay1(&self) -> &FcHsyncindelay1

0x1009 - Input video Horizontal active edge delay.

pub fn fc_hsyncinwidth0(&self) -> &FcHsyncinwidth0

0x100a - Input video Hsync active pulse width. Integer number of pixel clock cycles [0…511].

pub fn fc_hsyncinwidth1(&self) -> &FcHsyncinwidth1

0x100b - Input video Hsync active pulse width.

pub fn fc_vsyncindelay(&self) -> &FcVsyncindelay

0x100c - Input video Vsync active edge delay. Integer number of Hsync pulses from “de” non active edge of the last “de” valid period. [0…255].

pub fn fc_vsyncinwidth(&self) -> &FcVsyncinwidth

0x100d - Description: Input video Vsync active pulse width. Integer number of video lines [0…63].

pub fn fc_infreq0(&self) -> &FcInfreq0

0x100e - Video refresh rate in Hz*1E3 format. This register is provided for debug and informative purposes. The Hdmi_tx does not write any data to this register; the data written by software is not used by the Hdmi_tx.

pub fn fc_infreq1(&self) -> &FcInfreq1

0x100f - Video refresh rate in Hz*1E3 format. This register is provided for debug and informative purposes. The Hdmi_tx does not write any data to this register; the data written by software is not used by the Hdmi_tx.

pub fn fc_infreq2(&self) -> &FcInfreq2

0x1010 - Video refresh rate in Hz*1E3 format. This register is provided for debug and informative purposes. The Hdmi_tx does not write any data to this register; the data written by software is not used by the Hdmi_tx.

pub fn fc_ctrldur(&self) -> &FcCtrldur

0x1011 - Configuration of the control period minimum duration (minimum of 12 pixel clock cycles; refer to HDMI 1.4b specification). Integer number of pixel clocks cycles [0..223].

pub fn fc_exctrldur(&self) -> &FcExctrldur

0x1012 - Configuration of the extended control period minimum duration (minimum of 32 pixel clock cycles; refer to HDMI 1.4b specification). Integer number of pixel clocks cycles [0..223].

pub fn fc_exctrlspac(&self) -> &FcExctrlspac

0x1013 - Configuration of the maximum spacing between consecutive extended control periods (maximum of 50ms; refer to the applicable HDMI specification). When using the HDMI 2.0 supported features (HDMI_TX_20 = 1): generated spacing = (1/freq tmds clock)256512*(extctrlperiodspacing +1) else generated spacing = (1/freq tmds clock)256256*(extctrlperiodspacing +1)

pub fn fc_ch0pream(&self) -> &FcCh0pream

0x1014 - When in control mode, configures 8 bits that fill the channel 0 data lines not used to transmit the preamble (for more clarification, refer to the HDMI 1.4b specification).

pub fn fc_ch1pream(&self) -> &FcCh1pream

0x1015 - When in control mode, configures 6 bits that fill the channel 1 data lines not used to transmit the preamble (for more clarification, refer to the HDMI 1.4b specification).

pub fn fc_ch2pream(&self) -> &FcCh2pream

0x1016 - When in control mode, configures 6 bits that fill the channel 2 data lines not used to transmit the preamble (for more clarification, refer to the HDMI 1.4b specification).

pub fn fc_aviconf3(&self) -> &FcAviconf3

0x1017 - IT content type according to CEA the specification

pub fn fc_gcp(&self) -> &FcGcp

0x1018 - Value of “clear_avmute” in the GCP packet

pub fn fc_aviconf0(&self) -> &FcAviconf0

0x1019 - Y1,Y0 RGB or YCC indicator

pub fn fc_aviconf1(&self) -> &FcAviconf1

0x101a - Active aspect ratio

pub fn fc_aviconf2(&self) -> &FcAviconf2

0x101b - Non-uniform picture scaling

pub fn fc_avivid(&self) -> &FcAvivid

0x101c - Configures the AVI InfoFrame Video Identification code. For more information, refer to the CEA-861- E specification.

pub fn fc_avietb(&self, n: usize) -> &FcAvietb

0x101d - Defines the AVI InfoFrame End of Top Bar value. For more information, refer to the CEA-861-E specification.

pub fn fc_avietb_iter(&self) -> impl Iterator<Item = &FcAvietb>

Iterator for array of: 0x101d - Defines the AVI InfoFrame End of Top Bar value. For more information, refer to the CEA-861-E specification.

pub fn fc_avisbb(&self, n: usize) -> &FcAvisbb

0x101f - This register defines the AVI InfoFrame Start of Bottom Bar value. For more information, refer to the CEA-861-E specification.

pub fn fc_avisbb_iter(&self) -> impl Iterator<Item = &FcAvisbb>

Iterator for array of: 0x101f - This register defines the AVI InfoFrame Start of Bottom Bar value. For more information, refer to the CEA-861-E specification.

pub fn fc_avielb(&self, n: usize) -> &FcAvielb

0x1021 - This register defines the AVI InfoFrame End of Left Bar value. For more information, refer to the CEA- 861-E specification.

pub fn fc_avielb_iter(&self) -> impl Iterator<Item = &FcAvielb>

Iterator for array of: 0x1021 - This register defines the AVI InfoFrame End of Left Bar value. For more information, refer to the CEA- 861-E specification.

pub fn fc_avisrb(&self, n: usize) -> &FcAvisrb

0x1023 - This register defines the AVI InfoFrame Start of Right Bar value. For more information, refer to the CEA-861-E specification.

pub fn fc_avisrb_iter(&self) -> impl Iterator<Item = &FcAvisrb>

Iterator for array of: 0x1023 - This register defines the AVI InfoFrame Start of Right Bar value. For more information, refer to the CEA-861-E specification.

pub fn fc_audiconf0(&self) -> &FcAudiconf0

0x1025 - Coding Type

pub fn fc_audiconf1(&self) -> &FcAudiconf1

0x1026 - Sampling frequency

pub fn fc_audiconf2(&self) -> &FcAudiconf2

0x1027 - Channel allocation

pub fn fc_audiconf3(&self) -> &FcAudiconf3

0x1028 - Level shift value (for down mixing)

pub fn fc_vsdieeeid2(&self) -> &FcVsdieeeid2

0x1029 - This register configures the Vendor Specific InfoFrame IEEE registration identifier. For more information, refer to the CEA- 861-E specification.

pub fn fc_vsdsize(&self) -> &FcVsdsize

0x102a - Packet size as described in the HDMI Vendor Specific InfoFrame (from the HDMI specification).

pub fn fc_vsdieeeid1(&self) -> &FcVsdieeeid1

0x1030 - This register configures the Vendor Specific InfoFrame IEEE registration identifier. For more information, refer to the CEA-861-E specification.

pub fn fc_vsdieeeid0(&self) -> &FcVsdieeeid0

0x1031 - This register configures the Vendor Specific InfoFrame IEEE registration identifier. For more information, refer to the CEA-861-E specification.

pub fn fc_vsdpayload(&self, n: usize) -> &FcVsdpayload

0x1032..0x104a - Frame Composer VSI Packet Data Payload Register Array Configures the Vendor Specific infoFrame 24 bytes specific payload. For more information, refer to the CEA-861-E specification.

pub fn fc_vsdpayload_iter(&self) -> impl Iterator<Item = &FcVsdpayload>

Iterator for array of: 0x1032..0x104a - Frame Composer VSI Packet Data Payload Register Array Configures the Vendor Specific infoFrame 24 bytes specific payload. For more information, refer to the CEA-861-E specification.

pub fn fc_spdvendorname(&self, n: usize) -> &FcSpdvendorname

0x104a..0x1052 - Frame Composer SPD Packet Data Vendor Name Register Array Configures the Source Product Descriptor infoFrame 8 bytes Vendor name. For more information, refer to the CEA-861-E specification.

pub fn fc_spdvendorname_iter(&self) -> impl Iterator<Item = &FcSpdvendorname>

Iterator for array of: 0x104a..0x1052 - Frame Composer SPD Packet Data Vendor Name Register Array Configures the Source Product Descriptor infoFrame 8 bytes Vendor name. For more information, refer to the CEA-861-E specification.

pub fn fc_spdproductname(&self, n: usize) -> &FcSpdproductname

0x1052..0x1062 - Frame Composer SPD packet Data Product Name Register Array Configures the Source Product Descriptor infoFrame 16 bytes Product name. For more information, refer to the CEA-861-E specification.

pub fn fc_spdproductname_iter(&self) -> impl Iterator<Item = &FcSpdproductname>

Iterator for array of: 0x1052..0x1062 - Frame Composer SPD packet Data Product Name Register Array Configures the Source Product Descriptor infoFrame 16 bytes Product name. For more information, refer to the CEA-861-E specification.

pub fn fc_spddeviceinf(&self) -> &FcSpddeviceinf

0x1062 - Frame Composer SPD Packet Data Source Product Descriptor Register

pub fn fc_audsconf(&self) -> &FcAudsconf

0x1063 - Set the audio packet layout to be sent in the packet: 1b: layout 1 0b: layout 0 If HDMI_TX_20 is defined and register field fc_multistream_ctrl.fc_mas_packet_en is active, this bit has no effect.

pub fn fc_audsstat(&self) -> &FcAudsstat

0x1064 - Shows the data sample present indication of the last Audio sample packet sent by the HDMI Tx Controller. This register information is at TMDS clock rate.

pub fn fc_audsv(&self) -> &FcAudsv

0x1065 - Set validity bit “V” for Channel 0, Left

pub fn fc_audsu(&self) -> &FcAudsu

0x1066 - Set user bit “U” for Channel 0, Left

pub fn fc_audschnl0(&self) -> &FcAudschnl0

0x1067 - IEC Copyright indication

pub fn fc_audschnl1(&self) -> &FcAudschnl1

0x1068 - Category code

pub fn fc_audschnl2(&self) -> &FcAudschnl2

0x1069 - Source number

pub fn fc_audschnl3(&self) -> &FcAudschnl3

0x106a - Channel number for first right sample

pub fn fc_audschnl4(&self) -> &FcAudschnl4

0x106b - Channel number for third right sample

pub fn fc_audschnl5(&self) -> &FcAudschnl5

0x106c - Channel number for first left sample

pub fn fc_audschnl6(&self) -> &FcAudschnl6

0x106d - Channel number for third left sample

pub fn fc_audschnl7(&self) -> &FcAudschnl7

0x106e - Sampling frequency

pub fn fc_audschnl8(&self) -> &FcAudschnl8

0x106f - Word length configuration

pub fn fc_ctrlqhigh(&self) -> &FcCtrlqhigh

0x1073 - Configures the number of high priority packets or audio sample packets consecutively attended before checking low priority queue status. Valid range is from 5’d1 to 5’d31.

pub fn fc_ctrlqlow(&self) -> &FcCtrlqlow

0x1074 - Configures the number of low priority packets or null packets consecutively attended before checking high priority queue status or audio samples availability. Valid range is from 5’d1 to 5’d31.

pub fn fc_acp0(&self) -> &FcAcp0

0x1075 - Configures the ACP packet type.

pub fn fc_acp16(&self) -> &FcAcp16

0x1082 - Frame Composer ACP Packet Body Configuration Register 16

pub fn fc_acp15(&self) -> &FcAcp15

0x1083 - Frame Composer ACP Packet Body Configuration Register 15

pub fn fc_acp14(&self) -> &FcAcp14

0x1084 - Frame Composer ACP Packet Body Configuration Register 14

pub fn fc_acp13(&self) -> &FcAcp13

0x1085 - Frame Composer ACP Packet Body Configuration Register 13

pub fn fc_acp12(&self) -> &FcAcp12

0x1086 - Frame Composer ACP Packet Body Configuration Register 12

pub fn fc_acp11(&self) -> &FcAcp11

0x1087 - Frame Composer ACP Packet Body Configuration Register 11

pub fn fc_acp10(&self) -> &FcAcp10

0x1088 - Frame Composer ACP Packet Body Configuration Register 10

pub fn fc_acp9(&self) -> &FcAcp9

0x1089 - Frame Composer ACP Packet Body Configuration Register 9

pub fn fc_acp8(&self) -> &FcAcp8

0x108a - Frame Composer ACP Packet Body Configuration Register 8

pub fn fc_acp7(&self) -> &FcAcp7

0x108b - Frame Composer ACP Packet Body Configuration Register 7

pub fn fc_acp6(&self) -> &FcAcp6

0x108c - Frame Composer ACP Packet Body Configuration Register 6

pub fn fc_acp5(&self) -> &FcAcp5

0x108d - Frame Composer ACP Packet Body Configuration Register 5

pub fn fc_acp4(&self) -> &FcAcp4

0x108e - Frame Composer ACP Packet Body Configuration Register 4

pub fn fc_acp3(&self) -> &FcAcp3

0x108f - Frame Composer ACP Packet Body Configuration Register 3

pub fn fc_acp2(&self) -> &FcAcp2

0x1090 - Frame Composer ACP Packet Body Configuration Register 2

pub fn fc_acp1(&self) -> &FcAcp1

0x1091 - Frame Composer ACP Packet Body Configuration Register 1

pub fn fc_iscr1_0(&self) -> &FcIscr1_0

0x1092 - ISRC1 Indication of packet continuation (ISRC2 will be transmitted)

pub fn fc_iscr1_16(&self) -> &FcIscr1_16

0x1093 - Frame Composer ISRC1 Packet Body Register 16; configures ISRC1 packet body of the ISRC1 packet

pub fn fc_iscr1_15(&self) -> &FcIscr1_15

0x1094 - Frame Composer ISRC1 Packet Body Register 15

pub fn fc_iscr1_14(&self) -> &FcIscr1_14

0x1095 - Frame Composer ISRC1 Packet Body Register 14

pub fn fc_iscr1_13(&self) -> &FcIscr1_13

0x1096 - Frame Composer ISRC1 Packet Body Register 13

pub fn fc_iscr1_12(&self) -> &FcIscr1_12

0x1097 - Frame Composer ISRC1 Packet Body Register 12

pub fn fc_iscr1_11(&self) -> &FcIscr1_11

0x1098 - Frame Composer ISRC1 Packet Body Register 11

pub fn fc_iscr1_10(&self) -> &FcIscr1_10

0x1099 - Frame Composer ISRC1 Packet Body Register 10

pub fn fc_iscr1_9(&self) -> &FcIscr1_9

0x109a - Frame Composer ISRC1 Packet Body Register 9

pub fn fc_iscr1_8(&self) -> &FcIscr1_8

0x109b - Frame Composer ISRC1 Packet Body Register 8

pub fn fc_iscr1_7(&self) -> &FcIscr1_7

0x109c - Frame Composer ISRC1 Packet Body Register 7

pub fn fc_iscr1_6(&self) -> &FcIscr1_6

0x109d - Frame Composer ISRC1 Packet Body Register 6

pub fn fc_iscr1_5(&self) -> &FcIscr1_5

0x109e - Frame Composer ISRC1 Packet Body Register 5

pub fn fc_iscr1_4(&self) -> &FcIscr1_4

0x109f - Frame Composer ISRC1 Packet Body Register 4

pub fn fc_iscr1_3(&self) -> &FcIscr1_3

0x10a0 - Frame Composer ISRC1 Packet Body Register 3

pub fn fc_iscr1_2(&self) -> &FcIscr1_2

0x10a1 - Frame Composer ISRC1 Packet Body Register 2

pub fn fc_iscr1_1(&self) -> &FcIscr1_1

0x10a2 - Frame Composer ISRC1 Packet Body Register 1

pub fn fc_iscr2_15(&self) -> &FcIscr2_15

0x10a3 - Frame Composer ISRC2 Packet Body Register 15; configures the ISRC2 packet body of the ISRC2 packet

pub fn fc_iscr2_14(&self) -> &FcIscr2_14

0x10a4 - Frame Composer ISRC2 Packet Body Register 14

pub fn fc_iscr2_13(&self) -> &FcIscr2_13

0x10a5 - Frame Composer ISRC2 Packet Body Register 13

pub fn fc_iscr2_12(&self) -> &FcIscr2_12

0x10a6 - Frame Composer ISRC2 Packet Body Register 12

pub fn fc_iscr2_11(&self) -> &FcIscr2_11

0x10a7 - Frame Composer ISRC2 Packet Body Register 11

pub fn fc_iscr2_10(&self) -> &FcIscr2_10

0x10a8 - Frame Composer ISRC2 Packet Body Register 10

pub fn fc_iscr2_9(&self) -> &FcIscr2_9

0x10a9 - Frame Composer ISRC2 Packet Body Register 9

pub fn fc_iscr2_8(&self) -> &FcIscr2_8

0x10aa - Frame Composer ISRC2 Packet Body Register 8

pub fn fc_iscr2_7(&self) -> &FcIscr2_7

0x10ab - Frame Composer ISRC2 Packet Body Register 7

pub fn fc_iscr2_6(&self) -> &FcIscr2_6

0x10ac - Frame Composer ISRC2 Packet Body Register 6

pub fn fc_iscr2_5(&self) -> &FcIscr2_5

0x10ad - Frame Composer ISRC2 Packet Body Register 5

pub fn fc_iscr2_4(&self) -> &FcIscr2_4

0x10ae - Frame Composer ISRC2 Packet Body Register 4

pub fn fc_iscr2_3(&self) -> &FcIscr2_3

0x10af - Frame Composer ISRC2 Packet Body Register 3

pub fn fc_iscr2_2(&self) -> &FcIscr2_2

0x10b0 - Frame Composer ISRC2 Packet Body Register 2

pub fn fc_iscr2_1(&self) -> &FcIscr2_1

0x10b1 - Frame Composer ISRC2 Packet Body Register 1

pub fn fc_iscr2_0(&self) -> &FcIscr2_0

0x10b2 - Frame Composer ISRC2 Packet Body Register 0

pub fn fc_datauto0(&self) -> &FcDatauto0

0x10b3 - Enables ACP automatic packet scheduling

pub fn fc_datauto1(&self) -> &FcDatauto1

0x10b4 - Packet frame interpolation for automatic packet scheduling

pub fn fc_datauto2(&self) -> &FcDatauto2

0x10b5 - Packets line spacing, for automatic packet scheduling

pub fn fc_datman(&self) -> &FcDatman

0x10b6 - ACP packet

pub fn fc_datauto3(&self) -> &FcDatauto3

0x10b7 - Enables ACR packet insertion

pub fn fc_rdrb0(&self) -> &FcRdrb0

0x10b8 - ACR Frame interpolation

pub fn fc_rdrb1(&self) -> &FcRdrb1

0x10b9 - ACR packet line spacing

pub fn fc_rdrb2(&self) -> &FcRdrb2

0x10ba - Audio frame interpolation

pub fn fc_rdrb3(&self) -> &FcRdrb3

0x10bb - Audio packets line spacing

pub fn fc_rdrb4(&self) -> &FcRdrb4

0x10bc - Frames interpolated between GCP packets

pub fn fc_rdrb5(&self) -> &FcRdrb5

0x10bd - GCP packets line spacing

pub fn fc_rdrb6(&self) -> &FcRdrb6

0x10be - Frames interpolated between AVI packets

pub fn fc_rdrb7(&self) -> &FcRdrb7

0x10bf - AVI packets line spacing

pub fn fc_rdrb8(&self) -> &FcRdrb8

0x10c0 - AMP frame interpolation

pub fn fc_rdrb9(&self) -> &FcRdrb9

0x10c1 - AMP packets line spacing

pub fn fc_rdrb10(&self) -> &FcRdrb10

0x10c2 - NTSC VBI frame interpolation

pub fn fc_rdrb11(&self) -> &FcRdrb11

0x10c3 - NTSC VBI packets line spacing

pub fn fc_rdrb12(&self) -> &FcRdrb12

0x10c4 - Description: DRM frame interpolation

pub fn fc_rdrb13(&self) -> &FcRdrb13

0x10c5 - DRM packets line spacing

pub fn fc_mask0(&self) -> &FcMask0

0x10d2 - Mask bit for FC_INT0.NULL interrupt bit

pub fn fc_mask1(&self) -> &FcMask1

0x10d6 - Mask bit for FC_INT1.GCP interrupt bit

pub fn fc_mask2(&self) -> &FcMask2

0x10da - Mask bit for FC_INT2.HighPriority_overflow interrupt bit

pub fn fc_prconf(&self) -> &FcPrconf

0x10e0 - Configures the video pixel repetition ratio to be sent on the AVI InfoFrame. This value must be valid according to the HDMI specification. The output_pr_factor = incoming_pr_factor * (desired_pr_factor + 1) – 1. output_pr_factor[3:0] 0000b: No action. Not used. 0001b: Pixel sent two times (pixel repeated once) 0010b: Pixel sent three times 0011b: Pixel sent four times 0100b: Pixel sent five times 0101b: Pixel sent six times 0110b: Pixel sent seven times 0111b: Pixel sent eight times 1000b: Pixel sent nine times 1001b: Pixel sent 10 times Other: Reserved. Not used Note: When working in YCC422 video, the actual repetition of the stream is Incoming_pr_factor * (desired_pr_factor + 1). This calculation is done internally in the H13TCTRL and no hardware overflow protection is available. Care must be taken to avoid this result passes the maximum number of 10 pixels repeated because no HDMI support is available for this in the specification and the H13TPHY does not support this higher repetition values.

pub fn fc_scrambler_ctrl(&self) -> &FcScramblerCtrl

0x10e1 - When set (1’b1), this field activates the HDMI 2.0 scrambler feature. When disabled (1’b0) the scrambler feature is bypassed, placing Hdmi_tx in HDMI 1.4b compatible mode. To activate the scrambler feature, you must ensure that the quasi- static configuration bit fc_invidconf.HDCP_keepout is set (1’b1) at configuration time, before the required mc_swrstzreq.tmdsswrst_req reset request is issued. This is field can be changed in runtime.

pub fn fc_multistream_ctrl(&self) -> &FcMultistreamCtrl

0x10e2 - This field, when set (1’b1), activates the HDMI 2.0 Multi- Stream support. The audio stream present at the input of the Hdmi_tx controller is transported using Multi-Stream Audio Sample Packets.

pub fn fc_packet_tx_en(&self) -> &FcPacketTxEn

0x10e3 - ACR packet transmission control 1b: Transmission enabled 0b: Transmission disabled

pub fn fc_actspc_hdlr_cfg(&self) -> &FcActspcHdlrCfg

0x10e8 - Active Space Handler Control 1b: Fixed active space value mode enabled. During active space, a fixed value of 0xAA is applied to all TMDS channels. 0b: Fixed active space value mode disabled

pub fn fc_invact_2d_0(&self) -> &FcInvact2d0

0x10e9 - 2D Input video vertical active pixel region width. Number of 2D video vertical active lines [7:0].

pub fn fc_invact_2d_1(&self) -> &FcInvact2d1

0x10ea - 2D Input video vertical active pixel region width. Number of 2D video vertical active lines [11:8].

pub fn fc_gmd_stat(&self) -> &FcGmdStat

0x1100 - Gamut scheduling: Current Gamut packet sequence number

pub fn fc_gmd_en(&self) -> &FcGmdEn

0x1101 - Gamut Metadata packet transmission enable (1b)

pub fn fc_gmd_up(&self) -> &FcGmdUp

0x1102 - Gamut Metadata packet update

pub fn fc_gmd_conf(&self) -> &FcGmdConf

0x1103 - Number of line spacing between the transmitted GMD packets

pub fn fc_gmd_hb(&self) -> &FcGmdHb

0x1104 - Affected gamut sequence number

pub fn fc_gmd_pb(&self, n: usize) -> &FcGmdPb

0x1105..0x1121 - Frame Composer GMD Packet Body Register Array

pub fn fc_gmd_pb_iter(&self) -> impl Iterator<Item = &FcGmdPb>

Iterator for array of: 0x1105..0x1121 - Frame Composer GMD Packet Body Register Array

pub fn fc_amp_hb1(&self) -> &FcAmpHb1

0x1128 - Frame Composer AMP Packet Header Register 1

pub fn fc_amp_hb2(&self) -> &FcAmpHb2

0x1129 - Frame Composer AMP Packet Header Register 2

pub fn fc_amp_pb(&self, n: usize) -> &FcAmpPb

0x112a..0x1146 - Frame Composer AMP Packet Body Register Array

pub fn fc_amp_pb_iter(&self) -> impl Iterator<Item = &FcAmpPb>

Iterator for array of: 0x112a..0x1146 - Frame Composer AMP Packet Body Register Array

pub fn fc_nvbi_hb1(&self) -> &FcNvbiHb1

0x1148 - Frame Composer NTSC VBI Packet Header Register 1

pub fn fc_nvbi_hb2(&self) -> &FcNvbiHb2

0x1149 - Frame Composer NTSC VBI Packet Header Register 2

pub fn fc_nvbi_pb(&self, n: usize) -> &FcNvbiPb

0x114a..0x1165 - Frame Composer NTSC VBI Packet Body Register Array

pub fn fc_nvbi_pb_iter(&self) -> impl Iterator<Item = &FcNvbiPb>

Iterator for array of: 0x114a..0x1165 - Frame Composer NTSC VBI Packet Body Register Array

pub fn fc_drm_up(&self) -> &FcDrmUp

0x1167 - DRM packet update

pub fn fc_drm_hb(&self, n: usize) -> &FcDrmHb

0x1168 - Frame Composer DRM Packet Header Register Array

pub fn fc_drm_hb_iter(&self) -> impl Iterator<Item = &FcDrmHb>

Iterator for array of: 0x1168 - Frame Composer DRM Packet Header Register Array

pub fn fc_drm_pb(&self, n: usize) -> &FcDrmPb

0x116a..0x1185 - Frame Composer DRM Packet Body Register Array

pub fn fc_drm_pb_iter(&self) -> impl Iterator<Item = &FcDrmPb>

Iterator for array of: 0x116a..0x1185 - Frame Composer DRM Packet Body Register Array

pub fn fc_dbgforce(&self) -> &FcDbgforce

0x1200 - Force fixed video output with FC_DBGTMDSx register contents.

pub fn fc_dbgaud0ch0(&self) -> &FcDbgaud0ch0

0x1201 - Frame Composer Audio Data Channel 0 Register 0

pub fn fc_dbgaud1ch0(&self) -> &FcDbgaud1ch0

0x1202 - Frame Composer Audio Data Channel 0 Register 1

pub fn fc_dbgaud2ch0(&self) -> &FcDbgaud2ch0

0x1203 - Frame Composer Audio Data Channel 0 Register 2

pub fn fc_dbgaud0ch1(&self) -> &FcDbgaud0ch1

0x1204 - Frame Composer Audio Data Channel 1 Register 0

pub fn fc_dbgaud1ch1(&self) -> &FcDbgaud1ch1

0x1205 - Frame Composer Audio Data Channel 1 Register 1

pub fn fc_dbgaud2ch1(&self) -> &FcDbgaud2ch1

0x1206 - Frame Composer Audio Data Channel 1 Register 2

pub fn fc_dbgaud0ch2(&self) -> &FcDbgaud0ch2

0x1207 - Frame Composer Audio Data Channel 2 Register 0

pub fn fc_dbgaud1ch2(&self) -> &FcDbgaud1ch2

0x1208 - Frame Composer Audio Data Channel 2 Register 1

pub fn fc_dbgaud2ch2(&self) -> &FcDbgaud2ch2

0x1209 - Frame Composer Audio Data Channel 2 Register 2

pub fn fc_dbgaud0ch3(&self) -> &FcDbgaud0ch3

0x120a - Frame Composer Audio Data Channel 3 Register 0

pub fn fc_dbgaud1ch3(&self) -> &FcDbgaud1ch3

0x120b - Frame Composer Audio Data Channel 3 Register 1

pub fn fc_dbgaud2ch3(&self) -> &FcDbgaud2ch3

0x120c - Frame Composer Audio Data Channel 3 Register 2

pub fn fc_dbgaud0ch4(&self) -> &FcDbgaud0ch4

0x120d - Frame Composer Audio Data Channel 4 Register 0

pub fn fc_dbgaud1ch4(&self) -> &FcDbgaud1ch4

0x120e - Frame Composer Audio Data Channel 4 Register 1

pub fn fc_dbgaud2ch4(&self) -> &FcDbgaud2ch4

0x120f - Frame Composer Audio Data Channel 4 Register 2

pub fn fc_dbgaud0ch5(&self) -> &FcDbgaud0ch5

0x1210 - Frame Composer Audio Data Channel 5 Register 0

pub fn fc_dbgaud1ch5(&self) -> &FcDbgaud1ch5

0x1211 - Frame Composer Audio Data Channel 5 Register 1

pub fn fc_dbgaud2ch5(&self) -> &FcDbgaud2ch5

0x1212 - Frame Composer Audio Data Channel 5 Register 2

pub fn fc_dbgaud0ch6(&self) -> &FcDbgaud0ch6

0x1213 - Frame Composer Audio Data Channel 6 Register 0

pub fn fc_dbgaud1ch6(&self) -> &FcDbgaud1ch6

0x1214 - Frame Composer Audio Data Channel 6 Register 1

pub fn fc_dbgaud2ch6(&self) -> &FcDbgaud2ch6

0x1215 - Frame Composer Audio Data Channel 6 Register 2

pub fn fc_dbgaud0ch7(&self) -> &FcDbgaud0ch7

0x1216 - Frame Composer Audio Data Channel 7 Register 0

pub fn fc_dbgaud1ch7(&self) -> &FcDbgaud1ch7

0x1217 - Frame Composer Audio Data Channel 7 Register 1

pub fn fc_dbgaud2ch7(&self) -> &FcDbgaud2ch7

0x1218 - Frame Composer Audio Data Channel 7 Register 2

pub fn fc_dbgtmds(&self, n: usize) -> &FcDbgtmds

0x1219 - Frame Composer TMDS Data Channel 0 Register

pub fn fc_dbgtmds_iter(&self) -> impl Iterator<Item = &FcDbgtmds>

Iterator for array of: 0x1219 - Frame Composer TMDS Data Channel 0 Register

pub fn phy_conf0(&self) -> &PhyConf0

0x3000 - Select interface control.

pub fn phy_tst0(&self) -> &PhyTst0

0x3001 - Test Clock signal. Otherwise, this field is a “spare” bit with no associated functionality.

pub fn phy_tst1(&self) -> &PhyTst1

0x3002 - Test Data input Otherwise, this field is a “spare” bit with no associated functionality.

pub fn phy_tst2(&self) -> &PhyTst2

0x3003 - Test Data output. Otherwise, this field is a “spare” bit with no associated functionality.

pub fn phy_stat0(&self) -> &PhyStat0

0x3004 - Status bit. TX PHY PLL lock indication. You may need to mask or change polarity of this interrupt after it has became active.

pub fn phy_int0(&self) -> &PhyInt0

0x3005 - Interrupt indication bit. TX PHY PLL lock indication interrupt.

pub fn phy_mask0(&self) -> &PhyMask0

0x3006 - Mask bit for PHY_INT0.TX_PHY_LOCK interrupt bit

pub fn phy_pol0(&self) -> &PhyPol0

0x3007 - Polarity bit for PHY_INT0.TX_PHY_LOCK interrupt bit

pub fn phy_pclfreq0(&self) -> &PhyPclfreq0

0x3008 - Pixel Clock Frequency (pclk_freq[7:0]).

pub fn phy_pclfreq1(&self) -> &PhyPclfreq1

0x3009 - Pixel Clock Frequency (pclk_freq[9:8]).

pub fn phy_pllcfgfreq0(&self) -> &PhyPllcfgfreq0

0x300a - PLL Configuration Frequency (pllcfgfreq[7:0]).

pub fn phy_pllcfgfreq1(&self) -> &PhyPllcfgfreq1

0x300b - PLL Configuration Frequency (pllcfgfreq[15:8]).

pub fn phy_pllcfgfreq2(&self) -> &PhyPllcfgfreq2

0x300c - PLL Configuration Frequency (pllcfgfreq[23:16]).

pub fn phy_i2cm_slave(&self) -> &PhyI2cmSlave

0x3020 - Slave address to be sent during read and write operations. PHY Gen2 slave address: 7’h69 HEAC PHY slave address: 7’h49

pub fn phy_i2cm_address(&self) -> &PhyI2cmAddress

0x3021 - Register address for read and write operations

pub fn phy_i2cm_datao_1(&self) -> &PhyI2cmDatao1

0x3022 - Data MSB (datao[15:8]) to be written on register pointed by phy_i2cm_address [7:0].

pub fn phy_i2cm_datao_0(&self) -> &PhyI2cmDatao0

0x3023 - Data LSB (datao[7:0]) to be written on register pointed by phy_i2cm_address [7:0].

pub fn phy_i2cm_datai_1(&self) -> &PhyI2cmDatai1

0x3024 - Data MSB (datai[15:8]) read from register pointed by phy_i2cm_address[7:0].

pub fn phy_i2cm_datai_0(&self) -> &PhyI2cmDatai0

0x3025 - Data LSB (datai[7:0]) read from register pointed by phy_i2cm_address[7:0].

pub fn phy_i2cm_operation(&self) -> &PhyI2cmOperation

0x3026 - Read operation request

pub fn phy_i2cm_int(&self) -> &PhyI2cmInt

0x3027 - Operation done status bit. Marks the end of a read or write operation.

pub fn phy_i2cm_ctlint(&self) -> &PhyI2cmCtlint

0x3028 - Arbitration error interrupt bit Bits Name Attr Description {arbitration_interrupt = (arbitration_mask==0b) && (arbitration_status==arbitration_pol)} Note: This bit field is read by the sticky bits present on the ih_i2cmphy_stat0 register.

pub fn phy_i2cm_div(&self) -> &PhyI2cmDiv

0x3029 - Reserved as “spare” register with no associated functionality.

pub fn phy_i2cm_softrstz(&self) -> &PhyI2cmSoftrstz

0x302a - I2C Master Software Reset. Active by writing a zero and auto cleared to one in the following cycle.

pub fn phy_i2cm_ss_scl_hcnt_1_addr(&self) -> &PhyI2cmSsSclHcnt1Addr

0x302b - PHY I2C Slow Speed SCL High Level Control Register 1

pub fn phy_i2cm_ss_scl_hcnt_0_addr(&self) -> &PhyI2cmSsSclHcnt0Addr

0x302c - PHY I2C Slow Speed SCL High Level Control Register 0

pub fn phy_i2cm_ss_scl_lcnt_1_addr(&self) -> &PhyI2cmSsSclLcnt1Addr

0x302d - PHY I2C Slow Speed SCL Low Level Control Register 1

pub fn phy_i2cm_ss_scl_lcnt_0_addr(&self) -> &PhyI2cmSsSclLcnt0Addr

0x302e - PHY I2C Slow Speed SCL Low Level Control Register 0

pub fn phy_i2cm_fs_scl_hcnt_1_addr(&self) -> &PhyI2cmFsSclHcnt1Addr

0x302f - PHY I2C Fast Speed SCL High Level Control Register 1

pub fn phy_i2cm_fs_scl_hcnt_0_addr(&self) -> &PhyI2cmFsSclHcnt0Addr

0x3030 - PHY I2C Fast Speed SCL High Level Control Register Bits Name Attr Description 0

pub fn phy_i2cm_fs_scl_lcnt_1_addr(&self) -> &PhyI2cmFsSclLcnt1Addr

0x3031 - PHY I2C Fast Speed SCL Low Level Control Register 1

pub fn phy_i2cm_fs_scl_lcnt_0_addr(&self) -> &PhyI2cmFsSclLcnt0Addr

0x3032 - PHY I2C Fast Speed SCL Low Level Control Register 0

pub fn phy_i2cm_sda_hold(&self) -> &PhyI2cmSdaHold

0x3033 - Defines the number of SFR clock cycles to meet tHD:DAT (300 ns) osda_hold = round_to_high_integer (300 ns / (1/ isfrclk_frequency))

pub fn jtag_phy_config(&self) -> &JtagPhyConfig

0x3034 - Configures the JTAG PHY interface output pin Bits Name Attr Description JTAG_TRST_N when in internal control mode (iphy_ext_ctrl=1’b0) or ophyext_jtag_trst_n when PHY_EXTERNAL=1.

pub fn jtag_phy_tap_tck(&self) -> &JtagPhyTapTck

0x3035 - Configures the JTAG PHY interface pin JTAG_TCK when in internal control mode (iphy_ext_ctrl=1’b0) or ophyext_jtag_tck when PHY_EXTERNAL=1.

pub fn jtag_phy_tap_in(&self) -> &JtagPhyTapIn

0x3036 - Configures the JTAG PHY interface pin JTAG_TDI when in internal control mode (iphy_ext_ctrl=1’b0) or ophyext_jtag_tdi when PHY_EXTERNAL=1.

pub fn jtag_phy_tap_out(&self) -> &JtagPhyTapOut

0x3037 - Read JTAG PHY interface input pin JTAG_TDO when in internal control mode (iphy_ext_ctrl=1’b0) or Bits Name Attr Description iphyext_jtag_tdo when PHY_EXTERNAL=1 Value After Reset: 0x0 jtag_phy_addr Description: PHY JTAG Address Control Register Size: 8 bits Offset: 0x3038 Bits Name Attr Description 7:0 jtag_addr R/W Configures the JTAG PHY interface pin JTAG_ADDR[7:0] when in internal control mode (iphy_ext_ctrl=1’b0) or iphyext_jtag_addr[7:0] when PHY_EXTERNAL=1

pub fn jtag_phy_addr(&self) -> &JtagPhyAddr

0x3038 - Configures the JTAG PHY interface pin JTAG_ADDR[7:0] when in internal control mode (iphy_ext_ctrl=1’b0) or iphyext_jtag_addr[7:0] when PHY_EXTERNAL=1

pub fn aud_conf0(&self) -> &AudConf0

0x3100 - Action I2S_in_en[0]

• I2Sdata[0] enable I2S_in_en[1]
• I2Sdata[1] enable I2S_in_en[2]
• I2Sdata[2] enable I2S_in_en[3]
• I2Sdata[3] enable

pub fn aud_conf1(&self) -> &AudConf1

0x3101 - I2S input data width I2S_width[4:0] | Action 00000b-01111b | Not used 10000b | 16 bit data samples at input 10001b | 17 bit data samples at input 10010b | 18 bit data samples at input 10011b | 19 bit data samples at input 10100b | 20 bit data samples at input 10101b | 21 bit data samples at input 10110b | 22 bit data samples at input 10111b | 23 bit data samples at input 11000b | 24 bit data samples at input 11001b- 11111b | Not Used

pub fn aud_int(&self) -> &AudInt

0x3102 - Reserved for future use.

pub fn aud_conf2(&self) -> &AudConf2

0x3103 - I2S HBR Mode Enable. When enabled, the I2S audio stream is transmitted using HBR packets.

pub fn aud_n1(&self) -> &AudN1

0x3200 - HDMI Audio Clock Regenerator N value

pub fn aud_n2(&self) -> &AudN2

0x3201 - HDMI Audio Clock Regenerator N value

pub fn aud_n3(&self) -> &AudN3

0x3202 - HDMI Audio Clock Regenerator N value

pub fn aud_cts1(&self) -> &AudCts1

0x3203 - HDMI Audio Clock Regenerator CTS calculated value. This value can be manually set using the CTS_manual (AUD_CTS3) mechanism.

pub fn aud_cts2(&self) -> &AudCts2

0x3204 - HDMI Audio Clock Regenerator CTS calculated value. This value can be manually set using the CTS_manual (AUD_CTS3) mechanism.

pub fn aud_cts3(&self) -> &AudCts3

0x3205 - HDMI Audio Clock Regenerator CTS calculated value. This value can be manually set using the CTS_manual (AUD_CTS3) mechanism.

pub fn aud_inputclkfs(&self) -> &AudInputclkfs

0x3206 - Fs factor configuration: ifsfactor[2:0] | Audio Clock | Action 0 | 128xFs | If you select the Bypass SPDIF DRU unit in coreConsultant, the input audio clock (either I2S or SPDIF according to configuration) is used at the audio packetizer to calculate the CTS value and ACR packet insertion rate. | 256xFs | The input audio clock (I2S only) is divided by 2 and then used at audio packetizer to calculate the CTS value and ACR packet insertion rate. | 512xFs | The input audio clock (either I2S or SPDIF according to configuration) used divided by 4 and then used at the audio packetizer to calculate the CTS value and ACR packet insertion rate. Note: When the SPDIF interface is receiving an HBR audio stream (“Support for HBR over SDPIF” parameter must be enabled), it is required that the selected IFSFACTOR to be set at 512xFs in order to comply with the HDMI ACR requirements for HBR Bits Name Attr Description audio streams. | Reserved | 64xFs | The input audio clock (I2S only) is multiplied by 2 and then used at the audio packetizer to calculate the CTS value and ACR packet insertion rate. others | 128xFs | If you select the Bypass SPDIF DRU unit in coreConsultant, the input audio clock (either I2S or SPDIF according to configuration) is used at the audio packetizer to calculate the CTS value and ACR packet insertion rate. The SPDIF interface, for non HBR audio, requires that the configured oversampling value to be 128xFs when HTX_SPDIFBYPDRU is enabled and 512xFs if not. When the SPDIF interface is receiving HBR audio (HBR_ON_SPDIF must be enabled), in order to comply with the HDMI ACR requirements for HBR audio streams.

pub fn aud_cts_dither(&self) -> &AudCtsDither

0x3207 - Dither dividend (4’d1 if no CTS Dither). This field should be configured with the value of dividend from the HDMI specification.

pub fn aud_spdif0(&self) -> &AudSpdif0

0x3300 - Reserved as “spare” bit with no associated functionality.

pub fn aud_spdif1(&self) -> &AudSpdif1

0x3301 - When set to 1’b1, this bit field indicates that the input stream has a High Bit Rate (HBR) to be transmitted in HDMI HBR packets. When clear (1b’0), the audio is transmitted in HDMI AUDS packets.Note:< Otherwise, this field is a “spare” bit with no associated functionality.

pub fn aud_spdifint(&self) -> &AudSpdifint

0x3302 - Reserved for future use.

pub fn aud_spdifint1(&self) -> &AudSpdifint1

0x3303 - Reserved for future use.

pub fn aud_spdif2(&self) -> &AudSpdif2

0x3304 - Action SPDIF_in_en[0]

• ispdifdata[0] enable SPDIF_in_en[1]
• ispdifdata[1] enable SPDIF_in_en[2]
• ispdifdata[2] enable SPDIF_in_en[3]
• ispdifdata[3] enable

pub fn gp_conf0(&self) -> &GpConf0

0x3500 - Audio FIFOs software reset Writing 0b: no action taken Writing 1b: Resets all audio FIFOs Reading from this register always returns 0b. Note: If a FIFO reset request (via register write command) lands in the middle of an GPAUD audio transaction, the samples become misaligned (left-right sequence lost). As a solution, for each FIFO reset, an associated SPDIF reset must be issued (writing 8’h7F to MC_SWRSTZ register).

pub fn gp_conf1(&self) -> &GpConf1

0x3501 - Each bit controls the enabling of the respective audio channel. For instance, bit 1, when set (1’b1), the audio Channel 1 is enabled. When cleared, the referred channel is disabled.

pub fn gp_conf2(&self) -> &GpConf2

0x3502 - HBR packets enable. The Hdmi_tx sends the HBR packets. This bit is enabled when the audio frequency is higher than 192 kHz. If this bit is enabled, the number of channels configured in GP_CONF1 must be set to 8’hFF.

pub fn gp_mask(&self) -> &GpMask

0x3506 - FIFO full flag mask

pub fn ahb_dma_conf0(&self) -> &AhbDmaConf0

0x3600 - 1’b: Forces the burst mode to be fixed beat, incremental burst mode designated by the incr_type[1:0] signal. 0’b: Normal operation is unspecified length, incremental burst. It corresponds to INCR AHB burst mode.

pub fn ahb_dma_start(&self) -> &AhbDmaStart

0x3601 - Start DMA transaction This register is auto-cleared when the transfer operation is completed (done).

pub fn ahb_dma_stop(&self) -> &AhbDmaStop

0x3602 - Stop DMA transaction This register is auto-cleared when the transfer operation is stopped (done).

pub fn ahb_dma_thrsld(&self) -> &AhbDmaThrsld

0x3603 - FIFO medium threshold occupation value

pub fn ahb_dma_straddr_set0(&self, n: usize) -> &AhbDmaStraddrSet0

0x3604 - Defines init_addr[7:0] to initiate DMA burst transactions

pub fn ahb_dma_straddr_set0_iter( &self ) -> impl Iterator<Item = &AhbDmaStraddrSet0>

Iterator for array of: 0x3604 - Defines init_addr[7:0] to initiate DMA burst transactions

pub fn ahb_dma_stpaddr_set0(&self, n: usize) -> &AhbDmaStpaddrSet0

0x3608 - Defines final_addr[7:0] to end DMA burst transactions

pub fn ahb_dma_stpaddr_set0_iter( &self ) -> impl Iterator<Item = &AhbDmaStpaddrSet0>

Iterator for array of: 0x3608 - Defines final_addr[7:0] to end DMA burst transactions

pub fn ahb_dma_bstraddr(&self, n: usize) -> &AhbDmaBstraddr

0x360c - Start address for the current burst operation

pub fn ahb_dma_bstraddr_iter(&self) -> impl Iterator<Item = &AhbDmaBstraddr>

Iterator for array of: 0x360c - Start address for the current burst operation

pub fn ahb_dma_mblength0(&self) -> &AhbDmaMblength0

0x3610 - Requested burst length (mburstlength[7:0])

pub fn ahb_dma_mblength1(&self) -> &AhbDmaMblength1

0x3611 - Requested burst length

pub fn ahb_dma_mask(&self) -> &AhbDmaMask

0x3614 - Audio FIFO empty interrupt mask.

pub fn ahb_dma_conf1(&self) -> &AhbDmaConf1

0x3616 - Each bit controls the enabling of the respective audio channel. For instance, when bit 1 is set (1’b1) the audio Channel 1 is enabled. When cleared, the referred channel is disabled.

pub fn ahb_dma_buffmask(&self) -> &AhbDmaBuffmask

0x3619 - Buffer empty flag mask

pub fn ahb_dma_mask1(&self) -> &AhbDmaMask1

0x361b - AHB DMA FIFO overrun mask

pub fn ahb_dma_status(&self) -> &AhbDmaStatus

0x361c - Indicates the set of start and stop addresses currently used by the AHB audio DMA. If cleared (1’b0), the start and stop addresses configured in the address range 0x3604 to 0x360B are being used. When set (1’b1), the configurations at address range 0x3620 to 0x3627 are being used. This bit is always at zero when autostart_enable is cleared (1’b0).

pub fn ahb_dma_conf2(&self) -> &AhbDmaConf2

0x361d - Enables the AHB audio DMA auto-start feature

pub fn ahb_dma_straddr_set1(&self, n: usize) -> &AhbDmaStraddrSet1

0x3620 - Defines init_addr_1[7:0] to initiate DMA burst transactions

pub fn ahb_dma_straddr_set1_iter( &self ) -> impl Iterator<Item = &AhbDmaStraddrSet1>

Iterator for array of: 0x3620 - Defines init_addr_1[7:0] to initiate DMA burst transactions

pub fn ahb_dma_stpaddr_set1(&self, n: usize) -> &AhbDmaStpaddrSet1

0x3624 - Defines final_addr_1[7:0] to end DMA burst transactions

pub fn ahb_dma_stpaddr_set1_iter( &self ) -> impl Iterator<Item = &AhbDmaStpaddrSet1>

Iterator for array of: 0x3624 - Defines final_addr_1[7:0] to end DMA burst transactions

pub fn mc_clkdis(&self) -> &McClkdis

0x4001 - Audio Sampler clock synchronous disable signal.

pub fn mc_swrstzreq(&self) -> &McSwrstzreq

0x4002 - Pixel software reset request.

pub fn mc_opctrl(&self) -> &McOpctrl

0x4003 - Block HDCP bypass mechanism 1’b0: This is the default value. You can write to the hdcp_clkdisable bit of the register mc_clkdis and bypass HDCP by acting on the register mc_clkdis bit 6 (hdcp_clkdisable) 1’b1: You can still write to the hdcp_clkdisable bit of the register mc_clkdis but this action disables the HDCP module and blocks the bypass mechanism. The output data is frozen and the HDMI Tx and RX fail authentication. Once you set the value to 1’b1, you can change the value back to 1’b0 only by issuing a master reset to the Bits Name Attr Description Hdmi_tx. Otherwise, this field is a “spare” bit with no associated functionality.

pub fn mc_flowctrl(&self) -> &McFlowctrl

0x4004 - Video path Feed Through enable bit: 1b: Color Space Converter is in the video data path. 0b: Color Space Converter is bypassed (not in the video data path).

pub fn mc_phyrstz(&self) -> &McPhyrstz

0x4005 - HDMI Source PHY active low reset control for PHY GEN1, active high reset control for PHY GEN2.

pub fn mc_lockonclock(&self) -> &McLockonclock

0x4006 - CEC clock status. Indicates that the clock is present in the system. Cleared by WR 1 to this position.

pub fn mc_heacphy_rst(&self) -> &McHeacphyRst

0x4007 - HEAC PHY reset (active high)

pub fn mc_lockonclock_2(&self) -> &McLockonclock2

0x4009 - AHB audio DMA clock status. Indicates that the clock is present in the system. Cleared by WR 1 to this position.

pub fn mc_swrstzreq_2(&self) -> &McSwrstzreq2

0x400a - AHB audio DMA software reset request. Writing 1’b1 does not result in any action. Writing 1’b0 to this register resets all AHB audio logic.

pub fn mc_opsts(&self) -> &McOpsts

0x4010 - HDCP SNPS 2.2 versus 1.4 switch value status. 1’b0: HDCP 1.4 selected 1’b1: HDCP 2.2 selected

pub fn base_sfrdivlow(&self) -> &BaseSfrdivlow

0x4018 - SFR clock divider Low This register must be configured with the 8 least- significant bits of the value sfrclk frequency divided by 1000 (for example, for 27 MHz base_sfrdiv[14:0] = 27027). The configured data is used to generate a reference pulse of 1ms period that is needed by several timers within the controller.

pub fn base_sfrdivhigh(&self) -> &BaseSfrdivhigh

0x4019 - SFR clock divider High This register must be configured with the 7 most- significant bits of the value sfrclk frequency divided by 1000 (for example, for 27 MHz base_sfrdiv[14:0] = 27027). The configured data is used to generate a reference pulse of 1ms period that is needed by several timers within the controller.

pub fn csc_cfg(&self) -> &CscCfg

0x4100 - Chroma decimation configuration: decmode[1:0] | Chroma Decimation 00 | decimation disabled 01 | Hd (z) =1 10 | Hd(z)=1/ 4 + 1/2z^(-1 )+1/4 z^(-2) 11 | Hd(z)x2^(11)= -5+12z^(-2) - 22z^(- 4)+39z^(-8) +109z^(-10) -204z^(-12)+648z^(-14) + 1024z^(-15) +648z^(-16) - 204z^(-18) +109z^(-20)- 65z^(-22) +39z^(-24) - 22z^(-26) +12z^(- 28)-5z^(-30)

pub fn csc_scale(&self) -> &CscScale

0x4101 - Defines the cscscale[1:0] scale factor to apply to all coefficients in Color Space Conversion. This scale factor is expressed in the number of left shifts to apply to each of the coefficients, ranging from 0 to 2.

pub fn csc_coef_a1_msb(&self) -> &CscCoefA1Msb

0x4102 - Color Space Converter Matrix A1 Coefficient Register MSB

pub fn csc_coef_a1_lsb(&self) -> &CscCoefA1Lsb

0x4103 - Color Space Converter Matrix A1 Coefficient Register LSB

pub fn csc_coef_a2_msb(&self) -> &CscCoefA2Msb

0x4104 - Color Space Converter Matrix A2 Coefficient Register MSB

pub fn csc_coef_a2_lsb(&self) -> &CscCoefA2Lsb

0x4105 - Color Space Converter Matrix A2 Coefficient Register LSB

pub fn csc_coef_a3_msb(&self) -> &CscCoefA3Msb

0x4106 - Color Space Converter Matrix A3 Coefficient Register MSB

pub fn csc_coef_a3_lsb(&self) -> &CscCoefA3Lsb

0x4107 - Color Space Converter Matrix A3 Coefficient Register LSB

pub fn csc_coef_a4_msb(&self) -> &CscCoefA4Msb

0x4108 - Color Space Converter Matrix A4 Coefficient Register MSB

pub fn csc_coef_a4_lsb(&self) -> &CscCoefA4Lsb

0x4109 - Color Space Converter Matrix A4 Coefficient Register LSB

pub fn csc_coef_b1_msb(&self) -> &CscCoefB1Msb

0x410a - Color Space Converter Matrix B1 Coefficient Register MSB

pub fn csc_coef_b1_lsb(&self) -> &CscCoefB1Lsb

0x410b - Color Space Converter Matrix B1 Coefficient Register LSB

pub fn csc_coef_b2_msb(&self) -> &CscCoefB2Msb

0x410c - Color Space Converter Matrix B2 Coefficient Register MSB

pub fn csc_coef_b2_lsb(&self) -> &CscCoefB2Lsb

0x410d - Color Space Converter Matrix B2 Coefficient Register LSB

pub fn csc_coef_b3_msb(&self) -> &CscCoefB3Msb

0x410e - Color Space Converter Matrix B3 Coefficient Register MSB

pub fn csc_coef_b3_lsb(&self) -> &CscCoefB3Lsb

0x410f - Color Space Converter Matrix B3 Coefficient Register LSB

pub fn csc_coef_b4_msb(&self) -> &CscCoefB4Msb

0x4110 - Color Space Converter Matrix B4 Coefficient Register MSB

pub fn csc_coef_b4_lsb(&self) -> &CscCoefB4Lsb

0x4111 - Color Space Converter Matrix B4 Coefficient Register LSB

pub fn csc_coef_c1_msb(&self) -> &CscCoefC1Msb

0x4112 - Color Space Converter Matrix C1 Coefficient Register MSB

pub fn csc_coef_c1_lsb(&self) -> &CscCoefC1Lsb

0x4113 - Color Space Converter Matrix C1 Coefficient Register LSB

pub fn csc_coef_c2_msb(&self) -> &CscCoefC2Msb

0x4114 - Color Space Converter Matrix C2 Coefficient Register MSB

pub fn csc_coef_c2_lsb(&self) -> &CscCoefC2Lsb

0x4115 - Color Space Converter Matrix C2 Coefficient Register LSB

pub fn csc_coef_c3_msb(&self) -> &CscCoefC3Msb

0x4116 - Color Space Converter Matrix C3 Coefficient Register MSB

pub fn csc_coef_c3_lsb(&self) -> &CscCoefC3Lsb

0x4117 - Color Space Converter Matrix C3 Coefficient Register LSB

pub fn csc_coef_c4_msb(&self) -> &CscCoefC4Msb

0x4118 - Description: Color Space Converter Matrix C4 Coefficient Register MSB

pub fn csc_coef_c4_lsb(&self) -> &CscCoefC4Lsb

0x4119 - Color Space Converter Matrix C4 Coefficient Register LSB

pub fn csc_limit_up_msb(&self) -> &CscLimitUpMsb

0x411a - Color Space Converter Matrix Output Upper Limit Register MSB

pub fn csc_limit_up_lsb(&self) -> &CscLimitUpLsb

0x411b - Color Space Converter Matrix Output Upper Limit Register LSB

pub fn csc_limit_dn_msb(&self) -> &CscLimitDnMsb

0x411c - Color Space Converter Matrix output Down Limit Register MSB

pub fn csc_limit_dn_lsb(&self) -> &CscLimitDnLsb

0x411d - Color Space Converter Matrix Output Down Limit Register LSB

pub fn a_hdcpcfg0(&self) -> &AHdcpcfg0

0x5000 - Configures the transmitter to operate with a HDMI capable device or with a DVI device.

pub fn a_hdcpcfg1(&self) -> &AHdcpcfg1

0x5001 - Software reset signal, active by writing a zero and auto cleared to 1 in the following cycle.

pub fn a_hdcpobs0(&self) -> &AHdcpobs0

0x5002 - Informs that the current HDMI link has the HDCP protocol fully engaged.

pub fn a_hdcpobs1(&self) -> &AHdcpobs1

0x5003 - Observability register informs in which state the revocation machine is on.

pub fn a_hdcpobs2(&self) -> &AHdcpobs2

0x5004 - Observability register informs in which state the EESS machine is on.

pub fn a_hdcpobs3(&self) -> &AHdcpobs3

0x5005 - Register read from attached sink device: Bcap(0x40) bit 0.

pub fn a_apiintclr(&self) -> &AApiintclr

0x5006 - Clears the interruption related to KSV Attr grant for Read-Write access.

pub fn a_apiintstat(&self) -> &AApiintstat

0x5007 - Notifies that the KSV Attr as been guaranteed for Read-Write access.

pub fn a_apiintmsk(&self) -> &AApiintmsk

0x5008 - Masks the interruption related to KSV Attr grant for Read-Write access.

pub fn a_vidpolcfg(&self) -> &AVidpolcfg

0x5009 - Reserved as “spare” bit with no associated functionality.

pub fn a_oesswcfg(&self) -> &AOesswcfg

0x500a - HDCP OESS WOO Configuration Register

pub fn a_coreverlsb(&self) -> &ACoreverlsb

0x5014 - HDCP Controller Version Register LSB

pub fn a_corevermsb(&self) -> &ACorevermsb

0x5015 - HDCP Controller Version Register MSB

pub fn a_ksvmemctrl(&self) -> &AKsvmemctrl

0x5016 - Request access to the KSV memory; must be de- asserted after the access is completed by the system.

pub fn hdcp_bstatus(&self, n: usize) -> &HdcpBstatus

0x5020 - HDCP BSTATUS[15:0]. If Attr has not been granted (see register a_ksvmemctrl), the value read will be 8’hff.

pub fn hdcp_bstatus_iter(&self) -> impl Iterator<Item = &HdcpBstatus>

Iterator for array of: 0x5020 - HDCP BSTATUS[15:0]. If Attr has not been granted (see register a_ksvmemctrl), the value read will be 8’hff.

pub fn hdcp_m0(&self, n: usize) -> &HdcpM0

0x5022..0x502a - HDCP M0[32:0]. If Attr has not been granted (see register a_ksvmemctrl) , the value read will be 8’hff. These values are only available on a configuration that has the SHA1 calculation by software.

pub fn hdcp_m0_iter(&self) -> impl Iterator<Item = &HdcpM0>

Iterator for array of: 0x5022..0x502a - HDCP M0[32:0]. If Attr has not been granted (see register a_ksvmemctrl) , the value read will be 8’hff. These values are only available on a configuration that has the SHA1 calculation by software.

pub fn hdcp_ksv(&self, n: usize) -> &HdcpKsv

0x502a..0x52a5 - Sink KSV FIFO byte, ordered in little endian (byte at address 0x502a belongs to byte 0 of KSV0). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff. In this address space, 635 KSV FIFO bytes are mapped, which allow for 127 KSV values, each with 5 bytes (40 bits).

pub fn hdcp_ksv_iter(&self) -> impl Iterator<Item = &HdcpKsv>

Iterator for array of: 0x502a..0x52a5 - Sink KSV FIFO byte, ordered in little endian (byte at address 0x502a belongs to byte 0 of KSV0). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff. In this address space, 635 KSV FIFO bytes are mapped, which allow for 127 KSV values, each with 5 bytes (40 bits).

pub fn hdcp_vh(&self, n: usize) -> &HdcpVh

0x52a5..0x52b9 - Sink VH’ byte, ordered in little endian (byte at address 0x525a belongs to byte 0 of VH0). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff. In this address space 20 VH bytes are mapped, which allow for 5 VH values, each with 4 bytes (32bits).

pub fn hdcp_vh_iter(&self) -> impl Iterator<Item = &HdcpVh>

Iterator for array of: 0x52a5..0x52b9 - Sink VH’ byte, ordered in little endian (byte at address 0x525a belongs to byte 0 of VH0). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff. In this address space 20 VH bytes are mapped, which allow for 5 VH values, each with 4 bytes (32bits).

pub fn hdcp_revoc_size_0(&self) -> &HdcpRevocSize0

0x52b9 - Register containing the LSB of KSV list size (ksv_list_size[7:0]). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff.

pub fn hdcp_revoc_size_1(&self) -> &HdcpRevocSize1

0x52ba - Register containing the MSB of KSV list size (ksv_list_size[15:8]). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff.

pub fn hdcp_revoc_list(&self, n: usize) -> &HdcpRevocList

0x52bb..0x667f - Revocation KSV byte, ordered in little endian (byte at address 0x52bb belongs to byte 0 of the first revoked KSV). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff. In this address space 5060 revoked KSV bytes are mapped, which allow for 1012 KSV values, each with 5 bytes (40 bits).

pub fn hdcp_revoc_list_iter(&self) -> impl Iterator<Item = &HdcpRevocList>

Iterator for array of: 0x52bb..0x667f - Revocation KSV byte, ordered in little endian (byte at address 0x52bb belongs to byte 0 of the first revoked KSV). If Attr has not been granted (see register a_ksvmemctrl), the value read is 8’hff. In this address space 5060 revoked KSV bytes are mapped, which allow for 1012 KSV values, each with 5 bytes (40 bits).

pub fn hdcpreg_bksv0(&self) -> &HdcpregBksv0

0x7800 - Contains the value of BKSV[7:0].

pub fn hdcpreg_bksv1(&self) -> &HdcpregBksv1

0x7801 - Description: Contains the value of BKSV[15:8].

pub fn hdcpreg_bksv2(&self) -> &HdcpregBksv2

0x7802 - Contains the value of BKSV[23:16].

pub fn hdcpreg_bksv3(&self) -> &HdcpregBksv3

0x7803 - Contains the value of BKSV[31:24].

pub fn hdcpreg_bksv4(&self) -> &HdcpregBksv4

0x7804 - Contains the value of BKSV[39:32].

pub fn hdcpreg_anconf(&self) -> &HdcpregAnconf

0x7805 - When oanbypass=1, the value of AN used in the HDCP engine comes from the hdcpreg_an0 to hdcpreg_an7 registers. When oanbypass=0, the value of AN used in the HDCP engine comes from the random number input.

pub fn hdcpreg_an0(&self) -> &HdcpregAn0

0x7806 - Contains the value of AN[7:0]

pub fn hdcpreg_an1(&self) -> &HdcpregAn1

0x7807 - Contains the value of AN[15:8]

pub fn hdcpreg_an2(&self) -> &HdcpregAn2

0x7808 - Contains the value of AN[23:16]

pub fn hdcpreg_an3(&self) -> &HdcpregAn3

0x7809 - Contains the value of AN[31:24]

pub fn hdcpreg_an4(&self) -> &HdcpregAn4

0x780a - Contains the value of AN[39:32]

pub fn hdcpreg_an5(&self) -> &HdcpregAn5

0x780b - Contains the value of AN[47:40]

pub fn hdcpreg_an6(&self) -> &HdcpregAn6

0x780c - Contains the value of AN[55:48]

pub fn hdcpreg_an7(&self) -> &HdcpregAn7

0x780d - Contains the value of BKSV[63:56]

pub fn hdcpreg_rmlctl(&self) -> &HdcpregRmlctl

0x780e - When set (1’b1), this bit activates the decryption of the Device Private keys.

pub fn hdcpreg_rmlsts(&self) -> &HdcpregRmlsts

0x780f - Current Device Private Key being written plus one. Position 0 is occupied by the AKSV.

pub fn hdcpreg_seed0(&self) -> &HdcpregSeed0

0x7810 - Least significant byte of the decryption seed value (dpk_decrypt_seed[7:0]).

pub fn hdcpreg_seed1(&self) -> &HdcpregSeed1

0x7811 - Most significant byte of the decryption seed value (dpk_decrypt_seed[15:8]).

pub fn hdcpreg_dpk0(&self) -> &HdcpregDpk0

0x7812 - Byte of the encrypted DPK value. dpk[7:0] When this byte is written, a strobe signal is generated that triggers the decryption and/or storage of the DPK word on the DPK internal RAM memory.

pub fn hdcpreg_dpk1(&self) -> &HdcpregDpk1

0x7813 - Byte of the encrypted DPK value. dpk[15:8]

pub fn hdcpreg_dpk2(&self) -> &HdcpregDpk2

0x7814 - Byte of the encrypted DPK value. dpk[23:16]

pub fn hdcpreg_dpk3(&self) -> &HdcpregDpk3

0x7815 - Byte of the encrypted DPK value. dpk[31:24]

pub fn hdcpreg_dpk4(&self) -> &HdcpregDpk4

0x7816 - Byte of the encrypted DPK value. dpk[39:32]

pub fn hdcpreg_dpk5(&self) -> &HdcpregDpk5

0x7817 - Contains the value of DPK[x][47:40]

pub fn hdcpreg_dpk6(&self) -> &HdcpregDpk6

0x7818 - Contains the value of DPK[x][55:48]

pub fn hdcp22reg_id(&self) -> &Hdcp22regId

0x7900 - Reserved for future use.

pub fn hdcp22reg_ctrl(&self) -> &Hdcp22regCtrl

0x7904 - HDCP 2.2 switch lock 1’b0: Enables you to change the direction of the HDCP 2.2 versus 1.4 switch by using the hdcp22_ovr_en and hdcp22_ovr_val. 1’b1: You can still write to hdcp22_ovr_en and hdcp22_ovr_val but has no effect over the HDCP 2.2 versus 1.4 switch, that keeps as it was configured by hdcp22_ovr_en and hdcp22_ovr_val at the time the 1’b1 was written to this bit field. Once you set the value to 1’b1, you can change the value back to 1’b0 only by issuing a master reset to the Hdmi_tx.

pub fn hdcp22reg_ctrl1(&self) -> &Hdcp22regCtrl1

0x7905 - HDCP 2.2 versus 1.4 color depth override enable: 1’b0: The default 1’b0 value indicates that the color depth sent to the external interface is the one configured in the vp_pr_cd.color_depth register field. 1’b1: Although the used color depth for pixel encoding is defined by the field vp_pr_cd.color_depth register, the color depth sent to the external interface is the one defined in register field hdcp22reg_ctrl1.hdcp22_cd_ovr_val.

pub fn hdcp22reg_sts(&self) -> &Hdcp22regSts

0x7908 - HDCP 2.2 HPD external interface status after lock mechanism (hdcp22reg_ctrl.hdcp22_switch_lock, hdcp22reg_ctrl.hdcp22_ovr_en and hdcp22reg_ctrl.hdcp22_ovr_val). 1’b0: Sink not detected (HPD line clear ) 1’b1: Sink detected (HPD line set)

pub fn hdcp22reg_mask(&self) -> &Hdcp22regMask

0x790c - Active high interrupt mask to HDCP 2.2 capable rise interrupt status

pub fn hdcp22reg_stat(&self) -> &Hdcp22regStat

0x790d - HDCP 2.2 capable rise interrupt status sticky bit. Clear by Write 1 to this bit field

pub fn hdcp22reg_mute(&self) -> &Hdcp22regMute

0x790e - Active high interrupt mute to HDCP 2.2 capable rise interrupt status

pub fn cec_ctrl(&self) -> &CecCtrl

0x7d00 - 2’b00: Signal Free Time = 3-bit periods. Previous attempt to send frame is unsuccessful. 2’b01: Signal Free Time = 5-bit periods. New initiator wants to send a frame. 2’b10: Signal Free Time = 7-bit periods. Present initiator wants to send another frame immediately after its previous frame. (specification CEC 9.1). 2’b11: Illegal value. If software writes this value, hardware sets the value to the default 2’b01.

pub fn cec_mask(&self) -> &CecMask

0x7d02 - The current transmission is successful (for initiator only)

pub fn cec_addr_l(&self) -> &CecAddrL

0x7d05 - Logical address 0 - Device TV

pub fn cec_addr_h(&self) -> &CecAddrH

0x7d06 - Logical address 8 - Playback Device 2

pub fn cec_tx_cnt(&self) -> &CecTxCnt

0x7d07 - CEC Transmitter Counter register 5’d0: No data needs to be transmitted 5’d1: Frame size is 1 byte 5’d16: Frame size is 16 bytes

pub fn cec_rx_cnt(&self) -> &CecRxCnt

0x7d08 - CEC Receiver Counter register: 5’d0: No data received 5’d1: 1-byte data is received 5’d16: 16-byte data is received

pub fn cec_tx_data(&self, n: usize) -> &CecTxData

0x7d10..0x7d20 - Data byte[x], where x is 0 to 15

pub fn cec_tx_data_iter(&self) -> impl Iterator<Item = &CecTxData>

Iterator for array of: 0x7d10..0x7d20 - Data byte[x], where x is 0 to 15

pub fn cec_rx_data(&self, n: usize) -> &CecRxData

0x7d20..0x7d30 - Data byte[x], where x is 0 to 15

pub fn cec_rx_data_iter(&self) -> impl Iterator<Item = &CecRxData>

Iterator for array of: 0x7d20..0x7d30 - Data byte[x], where x is 0 to 15

pub fn cec_lock(&self) -> &CecLock

0x7d30 - When a frame is received, this bit would be active. The CEC controller answers to all the messages with NACK until the CPU writes it to ‘0’.

pub fn cec_wakeupctrl(&self) -> &CecWakeupctrl

0x7d31 - OPCODE 0x04 wake up enable

pub fn i2cm_slave(&self) -> &I2cmSlave

0x7e00 - Slave address to be sent during read and write normal operations.

pub fn i2cm_address(&self) -> &I2cmAddress

0x7e01 - Register address for read and write operations

pub fn i2cm_datao(&self) -> &I2cmDatao

0x7e02 - Data to be written on register pointed by address[7:0].

pub fn i2cm_datai(&self) -> &I2cmDatai

0x7e03 - Data read from register pointed by address[7:0].

pub fn i2cm_operation(&self) -> &I2cmOperation

0x7e04 - Single byte read operation request

pub fn i2cm_int(&self) -> &I2cmInt

0x7e05 - Reserved for future use.

pub fn i2cm_ctlint(&self) -> &I2cmCtlint

0x7e06 - Arbitration error interrupt mask signal.

pub fn i2cm_div(&self) -> &I2cmDiv

0x7e07 - Reserved as “spare” bit with no associated functionality.

pub fn i2cm_segaddr(&self) -> &I2cmSegaddr

0x7e08 - I2C DDC Segment Address Configuration Register

pub fn i2cm_softrstz(&self) -> &I2cmSoftrstz

0x7e09 - I2C Master Software Reset. Active by writing a zero and auto cleared to one in the following cycle.

pub fn i2cm_segptr(&self) -> &I2cmSegptr

0x7e0a - I2C DDC Segment Pointer Register

pub fn i2cm_ss_scl_hcnt_1_addr(&self) -> &I2cmSsSclHcnt1Addr

0x7e0b - I2C DDC Slow Speed SCL High Level Control Register 1

pub fn i2cm_ss_scl_hcnt_0_addr(&self) -> &I2cmSsSclHcnt0Addr

0x7e0c - I2C DDC Slow Speed SCL High Level Control Register 0

pub fn i2cm_ss_scl_lcnt_1_addr(&self) -> &I2cmSsSclLcnt1Addr

0x7e0d - I2C DDC Slow Speed SCL Low Level Control Register 1

pub fn i2cm_ss_scl_lcnt_0_addr(&self) -> &I2cmSsSclLcnt0Addr

0x7e0e - I2C DDC Slow Speed SCL Low Level Control Register 0

pub fn i2cm_fs_scl_hcnt_1_addr(&self) -> &I2cmFsSclHcnt1Addr

0x7e0f - I2C DDC Fast Speed SCL High Level Control Register 1

pub fn i2cm_fs_scl_hcnt_0_addr(&self) -> &I2cmFsSclHcnt0Addr

0x7e10 - I2C DDC Fast Speed SCL High Level Control Register 0

pub fn i2cm_fs_scl_lcnt_1_addr(&self) -> &I2cmFsSclLcnt1Addr

0x7e11 - I2C DDC Fast Speed SCL Low Level Control Register 1

pub fn i2cm_fs_scl_lcnt_0_addr(&self) -> &I2cmFsSclLcnt0Addr

0x7e12 - I2C DDC Fast Speed SCL Low Level Control Register 0

pub fn i2cm_sda_hold(&self) -> &I2cmSdaHold

0x7e13 - Defines the number of SFR clock cycles to meet tHD;DAT (300 ns) osda_hold = round_to_high_integer (300 ns / (1 / isfrclk_frequency))

pub fn i2cm_scdc_read_update(&self) -> &I2cmScdcReadUpdate

0x7e14 - When set to 1’b1, a SCDC Update Read is performed and the read data loaded into registers i2cm_scdc_update0 and i2cm_scdc_update1.

pub fn i2cm_read_buff0(&self) -> &I2cmReadBuff0

0x7e20 - Byte 0 of a I2C read buffer sequential read (from address i2cm_address)

pub fn i2cm_read_buff1(&self) -> &I2cmReadBuff1

0x7e21 - Byte 1 of a I2C read buffer sequential read (from address i2cm_address+1)

pub fn i2cm_read_buff2(&self) -> &I2cmReadBuff2

0x7e22 - Byte 2 of a I2C read buffer sequential read (from address i2cm_address+2)

pub fn i2cm_read_buff3(&self) -> &I2cmReadBuff3

0x7e23 - Byte 3 of a I2C read buffer sequential read (from address i2cm_address+3)

pub fn i2cm_read_buff4(&self) -> &I2cmReadBuff4

0x7e24 - Byte 4 of a I2C read buffer sequential read (from address i2cm_address+4)

pub fn i2cm_read_buff5(&self) -> &I2cmReadBuff5

0x7e25 - Byte 5 of a I2C read buffer sequential read (from address i2cm_address+5)

pub fn i2cm_read_buff6(&self) -> &I2cmReadBuff6

0x7e26 - Byte 6 of a I2C read buffer sequential read (from address i2cm_address+6)

pub fn i2cm_read_buff7(&self) -> &I2cmReadBuff7

0x7e27 - Byte 7 of a I2C read buffer sequential read (from address i2cm_address+7)

pub fn i2cm_scdc_update0(&self) -> &I2cmScdcUpdate0

0x7e30 - Byte 0 of a SCDC I2C update sequential read

pub fn i2cm_scdc_update1(&self) -> &I2cmScdcUpdate1

0x7e31 - Byte 1 of a SCDC I2C update sequential read Bits Name Attr Description

Trait Implementations

impl Debug for Hdmi

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for Hdmi

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for Hdmi