[][src]Struct riscy::RegVal

pub struct RegVal(_);

A struct for representing a value that can be held inside of a general purpose register (eg, x0, x1, ..., x32).

While all general purpose registers are 32-bits wide in rv32i, the interpretation of those bits depends on the operation in question. For example, some instructions (such as lw) treat registers values as signed integers, while other instructions (such as lwu) treat them as unsigned integers.

Therefore, riscy uses this type to prevent programmers from assuming one interpretation or the other, and instead, it forces them to explicitly cast any RegVal to the representation they need.

All immediate values used by the decode module (such as ImmS) can also be cast to RegVal.

// get the value of the first argument register, `a0` (also known as `x10`)
let value = riscv.reg(10);
println!("a0 = {} (as an unsigned integer)", u32::from(value));
println!("a0 = {} (as an   signed integer)", i32::from(value));

Several operations which correspond to register-register instructions (eg, add, xor), are provided as either methods or as traits.

let value1 = RegVal::from_u32(2);
let value2 = RegVal::from_u32(3);

// addition
println!("value1 + value2 = {}", u32::from(value1 + value2));

// bitwise exclusive or
println!("value1 ^ value2 = {}", u32::from(value1 ^ value2));

// left logical shift
println!("value1 << value2 = {}", u32::from(value1.shift_left_logical(value2));

Implementations

impl RegVal[src]

pub fn less_than_signed(&self, other: RegVal) -> bool[src]

Compares two RegVals, interpreting them both as signed integers.

pub fn less_than_unsigned(&self, other: RegVal) -> bool[src]

Compares two RegVals, interpreting them both as unsigned integers.

pub fn greater_than_equal_to_signed(&self, other: RegVal) -> bool[src]

Compares two RegVals, interpreting them both as signed integers.

pub fn greater_than_equal_to_unsigned(&self, other: RegVal) -> bool[src]

Compares two RegVals, interpreting them both as unsigned integers.

pub fn shift_left_logical(&self, other: RegVal) -> RegVal[src]

Does a logical left shift of this register by the value in another register.

A logical left shift is one where the vacant bits are all set to 0.

The value in other is interpreted as an unsigned integer.

The sll instruction (shift left logical) will only ever supply small values for other. The behavior of this function is only guaranteed for values that could come from that instruction.

pub fn shift_right_logical(&self, other: RegVal) -> RegVal[src]

Does a logical right shift of this register by the value in another register.

A logical right shift is one where the vacant bits are all set to 0. This is most common when the register value is interpreted as an unsigned integer, since it has the effect of dividing by 2 to the power of other.

The value in other is interpreted as an unsigned integer.

The srl instruction (shift right logical) will only ever supply small values for other. The behavior of this function is only guaranteed for values that could come from that instruction.

pub fn shift_right_arithmetic(&self, other: RegVal) -> RegVal[src]

Does an arithmetic right shift of this register by the value in another register.

An arithmetic right shift is one where the vacant bits are all set to a copy of the most signfint bit. This is most common when the register value is interpreted as a signed integer, since it has the effect of dividing by 2 to the power of other, while preserving the sign.

The value in other is interpreted as an unsigned integer.

The srl instruction (shift right logical) will only ever supply small values for other. The behavior of this function is only guaranteed for values that could come from that instruction.

pub fn from_u32(val: u32) -> RegVal[src]

pub fn from_i32(val: i32) -> RegVal[src]

pub fn from_addr(addr: Addr) -> RegVal[src]

pub fn to_u32(self) -> u32[src]

pub fn to_i32(self) -> i32[src]

pub fn to_addr(self) -> Addr[src]

Trait Implementations

impl Add<RegVal> for Addr[src]

type Output = Addr

The resulting type after applying the + operator.

impl Add<RegVal> for RegVal[src]

type Output = RegVal

The resulting type after applying the + operator.

impl AddAssign<RegVal> for Addr[src]

impl BitAnd<RegVal> for RegVal[src]

type Output = RegVal

The resulting type after applying the & operator.

impl BitOr<RegVal> for RegVal[src]

type Output = RegVal

The resulting type after applying the | operator.

impl BitXor<RegVal> for RegVal[src]

type Output = RegVal

The resulting type after applying the ^ operator.

impl Clone for RegVal[src]

impl Copy for RegVal[src]

impl Debug for RegVal[src]

impl Eq for RegVal[src]

impl From<Addr> for RegVal[src]

impl From<RegVal> for u32[src]

impl From<RegVal> for i32[src]

impl From<RegVal> for Addr[src]

impl From<i32> for RegVal[src]

impl From<u32> for RegVal[src]

impl Hash for RegVal[src]

impl PartialEq<RegVal> for RegVal[src]

impl StructuralEq for RegVal[src]

impl StructuralPartialEq for RegVal[src]

impl Sub<RegVal> for RegVal[src]

type Output = RegVal

The resulting type after applying the - operator.

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T> ToOwned for T where
    T: Clone
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type Owned = T

The resulting type after obtaining ownership.

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.