[][src]Enum riscy::Instruction

pub enum Instruction {
    Beq {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bne {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Blt {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bge {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bltu {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bgeu {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Jalr {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Jal {
        rd: Reg,
        imm: ImmJ,
    },
    Lui {
        rd: Reg,
        imm: ImmU,
    },
    Auipc {
        rd: Reg,
        imm: ImmU,
    },
    Addi {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Slti {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Sltiu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Xori {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Ori {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Andi {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Slli {
        rd: Reg,
        rs1: Reg,
        shamt: ImmI,
    },
    Srli {
        rd: Reg,
        rs1: Reg,
        shamt: ImmI,
    },
    Srai {
        rd: Reg,
        rs1: Reg,
        shamt: ImmI,
    },
    Add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sub {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sll {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slt {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sltu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sra {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Or {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    And {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Lb {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lh {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lw {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lbu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lhu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lwu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Sb {
        imm: ImmS,
        rs1: Reg,
        rs2: Reg,
    },
    Sh {
        imm: ImmS,
        rs1: Reg,
        rs2: Reg,
    },
    Sw {
        imm: ImmS,
        rs1: Reg,
        rs2: Reg,
    },
    Fence {
        rd: Reg,
    },
    FenceI {
        rd: Reg,
    },
    ECall,
    EBreak,
}

A struct for representing a fully decoded r32i instruction. Each variant matches an assembly instruction.

Note that pseudo-instructions, such as li (load immediate) or mv (move), are short-hands used by RISC-V assemblers for short, common sequences of basic instructions. This struct only the basic instructions themselves, and so it does not list any pseudo-instructions.

Variants

Beq

Fields of Beq

rs1: Regrs2: Regimm: ImmB
Bne

Fields of Bne

rs1: Regrs2: Regimm: ImmB
Blt

Fields of Blt

rs1: Regrs2: Regimm: ImmB
Bge

Fields of Bge

rs1: Regrs2: Regimm: ImmB
Bltu

Fields of Bltu

rs1: Regrs2: Regimm: ImmB
Bgeu

Fields of Bgeu

rs1: Regrs2: Regimm: ImmB
Jalr

Fields of Jalr

rd: Regrs1: Regimm: ImmI
Jal

Fields of Jal

rd: Regimm: ImmJ
Lui

Fields of Lui

rd: Regimm: ImmU
Auipc

Fields of Auipc

rd: Regimm: ImmU
Addi

Fields of Addi

rd: Regrs1: Regimm: ImmI
Slti

Fields of Slti

rd: Regrs1: Regimm: ImmI
Sltiu

Fields of Sltiu

rd: Regrs1: Regimm: ImmI
Xori

Fields of Xori

rd: Regrs1: Regimm: ImmI
Ori

Fields of Ori

rd: Regrs1: Regimm: ImmI
Andi

Fields of Andi

rd: Regrs1: Regimm: ImmI
Slli

Fields of Slli

rd: Regrs1: Regshamt: ImmI
Srli

Fields of Srli

rd: Regrs1: Regshamt: ImmI
Srai

Fields of Srai

rd: Regrs1: Regshamt: ImmI
Add

Fields of Add

rd: Regrs1: Regrs2: Reg
Sub

Fields of Sub

rd: Regrs1: Regrs2: Reg
Sll

Fields of Sll

rd: Regrs1: Regrs2: Reg
Slt

Fields of Slt

rd: Regrs1: Regrs2: Reg
Sltu

Fields of Sltu

rd: Regrs1: Regrs2: Reg
Xor

Fields of Xor

rd: Regrs1: Regrs2: Reg
Srl

Fields of Srl

rd: Regrs1: Regrs2: Reg
Sra

Fields of Sra

rd: Regrs1: Regrs2: Reg
Or

Fields of Or

rd: Regrs1: Regrs2: Reg
And

Fields of And

rd: Regrs1: Regrs2: Reg
Lb

Fields of Lb

rd: Regrs1: Regimm: ImmI
Lh

Fields of Lh

rd: Regrs1: Regimm: ImmI
Lw

Fields of Lw

rd: Regrs1: Regimm: ImmI
Lbu

Fields of Lbu

rd: Regrs1: Regimm: ImmI
Lhu

Fields of Lhu

rd: Regrs1: Regimm: ImmI
Lwu

Fields of Lwu

rd: Regrs1: Regimm: ImmI
Sb

Fields of Sb

imm: ImmSrs1: Regrs2: Reg
Sh

Fields of Sh

imm: ImmSrs1: Regrs2: Reg
Sw

Fields of Sw

imm: ImmSrs1: Regrs2: Reg
Fence

Fields of Fence

rd: Reg
FenceI

Fields of FenceI

rd: Reg
ECall
EBreak

Trait Implementations

impl Clone for Instruction[src]

impl Copy for Instruction[src]

impl Debug for Instruction[src]

impl Display for Instruction[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> ToOwned for T where
    T: Clone
[src]

type Owned = T

The resulting type after obtaining ownership.

impl<T> ToString for T where
    T: Display + ?Sized
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.