Enum Compressed

Source

pub enum Compressed {
Show 47 variants    UNIMP,
    C_LWSP {
        rd: u32,
        offset: i32,
    },
    C_LDSP {
        rd: u32,
        offset: i32,
    },
    C_LQSP {
        rd: u32,
        offset: i32,
    },
    C_FLWSP {
        frd: u32,
        offset: i32,
    },
    C_FLDSP {
        frd: u32,
        offset: i32,
    },
    C_SWSP {
        rs2: u32,
        offset: i32,
    },
    C_SDSP {
        rs2: u32,
        offset: i32,
    },
    C_SQSP {
        rs2: u32,
        offset: i32,
    },
    C_FSWSP {
        frs2: u32,
        offset: i32,
    },
    C_FSDSP {
        frs2: u32,
        offset: i32,
    },
    C_LW {
        rd: u32,
        rs1: u32,
        offset: i32,
    },
    C_LD {
        rd: u32,
        rs1: u32,
        offset: i32,
    },
    C_LQ {
        rd: u32,
        rs1: u32,
        offset: i32,
    },
    C_FLW {
        frd: u32,
        rs1: u32,
        offset: i32,
    },
    C_FLD {
        frd: u32,
        rs1: u32,
        offset: i32,
    },
    C_SW {
        rs1: u32,
        rs2: u32,
        offset: i32,
    },
    C_SD {
        rs1: u32,
        rs2: u32,
        offset: i32,
    },
    C_SQ {
        rs1: u32,
        rs2: u32,
        offset: i32,
    },
    C_FSW {
        rs1: u32,
        frs2: u32,
        offset: i32,
    },
    C_FSD {
        rs1: u32,
        frs2: u32,
        offset: i32,
    },
    C_J {
        offset: i32,
    },
    C_JAL {
        offset: i32,
    },
    C_JR {
        rs1: u32,
    },
    C_JALR {
        rs1: u32,
    },
    C_BEQZ {
        rs1: u32,
        offset: i32,
    },
    C_BNEZ {
        rs1: u32,
        offset: i32,
    },
    C_LI {
        rd: u32,
        imm: i32,
    },
    C_LUI {
        rd: u32,
        imm: u32,
    },
    C_ADDI {
        rd: u32,
        imm: i32,
    },
    C_ADDIW {
        rd: u32,
        imm: i32,
    },
    C_ADDI16SP {
        imm: i32,
    },
    C_ADDI4SPN {
        rd: u32,
        imm: i32,
    },
    C_SLLI {
        rd: u32,
        shamt: u32,
    },
    C_SRLI {
        rd: u32,
        shamt: u32,
    },
    C_SRAI {
        rd: u32,
        shamt: u32,
    },
    C_ANDI {
        rd: u32,
        imm: i32,
    },
    C_MV {
        rd: u32,
        rs2: u32,
    },
    C_ADD {
        rd: u32,
        rs2: u32,
    },
    C_AND {
        rd: u32,
        rs2: u32,
    },
    C_OR {
        rd: u32,
        rs2: u32,
    },
    C_XOR {
        rd: u32,
        rs2: u32,
    },
    C_SUB {
        rd: u32,
        rs2: u32,
    },
    C_ADDW {
        rd: u32,
        rs2: u32,
    },
    C_SUBW {
        rd: u32,
        rs2: u32,
    },
    C_NOP,
    C_EBREAK,
}

Expand description

Compressed RISC-V instruction.

Compressed instructions can be decompressed using Instruction::from.

Instruction arguments are all in their decoded forms, meaning correctly scaled and sign extended. Registers are normalised. Their names are as they appear in specifications (for the most part), and include:

rd, rs1, `rs2``: destination and source registers.
frd, frs2: destination and source floating point registers.
offset, imm, shamt: numerical offsets, immediates, and shift amounts.
pred, succ: predecessor and successor IORW (input, output, read, write) flags.
rm: floating point rounding mode.
rl, aq: atomic release and acquire flags.

Assumed and redundant flags are not repeated, i.e. rd is not stored for c.swsp as it’s always sp (x2) and only rd is stored for c.addi as rs1 is always the same.