Instruction

riscv_codec::instruction

Enum Instruction 

Source 
pub enum Instruction {

Show 156 variants    Lui {
        dest: IRegister,
        imm: UImmediate,
    },
    Auipc {
        dest: IRegister,
        imm: UImmediate,
    },
    Jal {
        dest: IRegister,
        offset: JImmediate,
    },
    Jalr {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Beq {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    Bne {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    Blt {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    Bge {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    Bltu {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    Bgeu {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    Lb {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Lh {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Lw {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Lbu {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Lhu {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Sb {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    Sh {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    Sw {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    Addi {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Slti {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Sltiu {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Xori {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Ori {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Andi {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Slli {
        dest: IRegister,
        src: IRegister,
        shamt: Shamt,
    },
    Srli {
        dest: IRegister,
        src: IRegister,
        shamt: Shamt,
    },
    Srai {
        dest: IRegister,
        src: IRegister,
        shamt: Shamt,
    },
    Add {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Sub {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Sll {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Slt {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Sltu {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Xor {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Srl {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Sra {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Or {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    And {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Fence {
        rd: IRegister,
        rs1: IRegister,
        ops: u8,
        fm: u8,
    },
    Ecall,
    Ebreak,
    Lwu {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Ld {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Sd {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    Addiw {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    Slliw {
        dest: IRegister,
        src: IRegister,
        shamt: ShamtW,
    },
    Srliw {
        dest: IRegister,
        src: IRegister,
        shamt: ShamtW,
    },
    Sraiw {
        dest: IRegister,
        src: IRegister,
        shamt: ShamtW,
    },
    Addw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Subw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Sllw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Srlw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Sraw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Mul {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Mulh {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Mulhsu {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Mulhu {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Div {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Divu {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Rem {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Remu {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Mulw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Divw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Divuw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Remw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    Remuw {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    LrW {
        dest: IRegister,
        addr: IRegister,
        aq: bool,
        rl: bool,
    },
    ScW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoswapW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoaddW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoxorW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoandW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoorW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmominW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmomaxW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmominuW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmomaxuW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    LrD {
        dest: IRegister,
        addr: IRegister,
        aq: bool,
        rl: bool,
    },
    ScD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoswapD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoaddD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoxorD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoandD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmoorD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmominD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmomaxD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmominuD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AmomaxuD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    Flw {
        dest: FRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Fsw {
        base: IRegister,
        src: FRegister,
        offset: SImmediate,
    },
    FmaddS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FmsubS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FnmsubS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FnmaddS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FaddS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FsubS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FmulS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FdivS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FsqrtS {
        dest: FRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FsgnjS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FsgnjnS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FsgnjxS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FminS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FmaxS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FcvtWS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FcvtWuS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FmvXW {
        dest: IRegister,
        src: FRegister,
    },
    FeqS {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FltS {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FleS {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FclassS {
        dest: IRegister,
        src: FRegister,
    },
    FcvtSW {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FcvtSWu {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FmvWX {
        dest: FRegister,
        src: IRegister,
    },
    FcvtLS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FcvtLuS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FcvtSL {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FcvtSLu {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    Csrrw {
        dest: IRegister,
        src: IRegister,
        csr: CSR,
    },
    Csrrs {
        dest: IRegister,
        src: IRegister,
        csr: CSR,
    },
    Csrrc {
        dest: IRegister,
        src: IRegister,
        csr: CSR,
    },
    Csrrwi {
        dest: IRegister,
        imm: CSRImmediate,
        csr: CSR,
    },
    Csrrsi {
        dest: IRegister,
        imm: CSRImmediate,
        csr: CSR,
    },
    Csrrci {
        dest: IRegister,
        imm: CSRImmediate,
        csr: CSR,
    },
    FenceI,
    Fld {
        dest: FRegister,
        base: IRegister,
        offset: IImmediate,
    },
    Fsd {
        src: FRegister,
        base: IRegister,
        offset: SImmediate,
    },
    FmaddD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FmsubD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FnmaddD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FnmsubD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FaddD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FsubD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FmulD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FdivD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FsqrtD {
        dest: FRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FsgnjD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FsgnjnD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FsgnjxD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FminD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FmaxD {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FcvtSD {
        dest: FRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FcvtDS {
        dest: FRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FeqD {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FltD {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FleD {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FclassD {
        dest: IRegister,
        src1: FRegister,
    },
    FcvtWD {
        dest: IRegister,
        src1: FRegister,
        rm: RoundingMode,
    },
    FcvtWuD {
        dest: IRegister,
        src1: FRegister,
        rm: RoundingMode,
    },
    FcvtDW {
        dest: FRegister,
        src1: IRegister,
        rm: RoundingMode,
    },
    FcvtDWu {
        dest: FRegister,
        src1: IRegister,
        rm: RoundingMode,
    },
    FcvtLD {
        dest: IRegister,
        src1: FRegister,
        rm: RoundingMode,
    },
    FcvtLuD {
        dest: IRegister,
        src1: FRegister,
        rm: RoundingMode,
    },
    FmvXD {
        dest: IRegister,
        src: FRegister,
    },
    FcvtDL {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FcvtDLu {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FmvDX {
        dest: FRegister,
        src: IRegister,
    },

}

Variants§

§

Lui

Load upper immediate

Fields

§dest: IRegister
§imm: UImmediate
§

Auipc

Add upper immediate to PC

Fields

§dest: IRegister
§imm: UImmediate
§

Jal

Jump and Link

Fields

§dest: IRegister
§offset: JImmediate
§

Jalr

Jump and Link Register

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Beq

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

Bne

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

Blt

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

Bge

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

Bltu

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

Bgeu

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

Lb

Load Byte

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Lh

Load Halfword

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Lw

Load Word

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Lbu

Load Byte Unsigned

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Lhu

Load Halfword Unsigned

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Sb

Store Byte

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

Sh

Store Halfword

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

Sw

Store Word

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

Addi

§

Slti

§

Sltiu

§

Xori

§

Ori

§

Andi

§

Slli

Left Shift Immediate

Fields

§dest: IRegister
§src: IRegister
§shamt: Shamt
§

Srli

Logical Right Shift Immediate

Fields

§dest: IRegister
§src: IRegister
§shamt: Shamt
§

Srai

Arithmetic Right Shift Immediate

Fields

§dest: IRegister
§src: IRegister
§shamt: Shamt
§

Add

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Sub

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Sll

Left Shift

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Slt

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Sltu

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Xor

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Srl

Logical Right Shift Immediate

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Sra

Arithmetic Right Shift Immediate

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Or

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

And

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Fence

Fields

§rd: IRegister
§rs1: IRegister
§ops: u8
§fm: u8
§

Ecall

§

Ebreak

§

Lwu

Load Word Unsigned

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Ld

Load Doubleword

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

Sd

Store Doubleword

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

Addiw

Add Immediate (word)

§

Slliw

Left Shift Immediate (word)

Fields

§dest: IRegister
§src: IRegister
§shamt: ShamtW
§

Srliw

Logical Right Shift Immediate (word)

Fields

§dest: IRegister
§src: IRegister
§shamt: ShamtW
§

Sraiw

Arithmetic Right Shift Immediate (word)

Fields

§dest: IRegister
§src: IRegister
§shamt: ShamtW
§

Addw

Add (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Subw

Subtract (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Sllw

Left Shift (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Srlw

Logical Right Shift (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Sraw

Arithmetic Right Shift (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Mul

Multiply

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Mulh

Multiply (High bits)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Mulhsu

Multiply Signed-Unsigned (High bits)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Mulhu

Multiply Unsigned (High)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Div

Divide

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Divu

Divide (Unsigned)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Rem

Remainder

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Remu

Remainder (Unsigned)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Mulw

Multiply Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Divw

Divide Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Divuw

Divide Unsigned Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Remw

Remainder Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

Remuw

Remainder Unsigned Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

LrW

Load Reserved Word

Fields

§dest: IRegister
§addr: IRegister
§aq: bool
§rl: bool
§

ScW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoswapW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoaddW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoxorW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoandW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoorW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmominW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmomaxW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmominuW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmomaxuW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

LrD

Fields

§dest: IRegister
§addr: IRegister
§aq: bool
§rl: bool
§

ScD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoswapD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoaddD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoxorD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoandD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmoorD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmominD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmomaxD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmominuD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AmomaxuD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

Flw

Fields

§dest: FRegister
§base: IRegister
§offset: IImmediate
§

Fsw

Fields

§base: IRegister
§src: FRegister
§offset: SImmediate
§

FmaddS

§

FmsubS

§

FnmsubS

§

FnmaddS

§

FaddS

§

FsubS

§

FmulS

§

FdivS

§

FsqrtS

§

FsgnjS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FsgnjnS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FsgnjxS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FminS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FmaxS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FcvtWS

§

FcvtWuS

§

FmvXW

Fields

§dest: IRegister
§src: FRegister
§

FeqS

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FltS

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FleS

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FclassS

Fields

§dest: IRegister
§src: FRegister
§

FcvtSW

§

FcvtSWu

§

FmvWX

Fields

§dest: FRegister
§src: IRegister
§

FcvtLS

§

FcvtLuS

§

FcvtSL

§

FcvtSLu

§

Csrrw

Fields

§dest: IRegister
§src: IRegister
§csr: CSR
§

Csrrs

Fields

§dest: IRegister
§src: IRegister
§csr: CSR
§

Csrrc

Fields

§dest: IRegister
§src: IRegister
§csr: CSR
§

Csrrwi

Fields

§dest: IRegister
§imm: CSRImmediate
§csr: CSR
§

Csrrsi

Fields

§dest: IRegister
§imm: CSRImmediate
§csr: CSR
§

Csrrci

Fields

§dest: IRegister
§imm: CSRImmediate
§csr: CSR
§

FenceI

§

Fld

Fields

§dest: FRegister
§base: IRegister
§offset: IImmediate
§

Fsd

Fields

§src: FRegister
§base: IRegister
§offset: SImmediate
§

FmaddD

§

FmsubD

§

FnmaddD

§

FnmsubD

§

FaddD

§

FsubD

§

FmulD

§

FdivD

§

FsqrtD

§

FsgnjD

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FsgnjnD

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FsgnjxD

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FminD

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FmaxD

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FcvtSD

§

FcvtDS

§

FeqD

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FltD

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FleD

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FclassD

Fields

§dest: IRegister
§src1: FRegister
§

FcvtWD

§

FcvtWuD

§

FcvtDW

§

FcvtDWu

§

FcvtLD

§

FcvtLuD

§

FmvXD

Fields

§dest: IRegister
§src: FRegister
§

FcvtDL

§

FcvtDLu

§

FmvDX

Fields

§dest: FRegister
§src: IRegister

Implementations§

Source§

impl Instruction

Source

pub fn decode(instruction: u32) -> Result<Instruction, String>

Constructs an Instruction from it’s machine code representation.

Examples found in repository?
examples/simple.rs (line 9)
2fn main() {
3    // instruction can be assembled from strings
4    let instr: Instruction = assemble_line("addi t0, t1, 1024").unwrap().i();
5    // and disassembled
6    println!("assembled instruction: {}", instr);
7
8    // instructions can also be decoded from binary
9    let instr2 = Instruction::decode(0xe0058513).unwrap();
10
11    // and encoded
12    assert_eq!(Instruction::encode(&instr2), 0xe0058513);
13
14    let instr2 = assemble_line("fcvt.lu.s zero,ft0,rne").unwrap().i();
15    println!("assembled instruction: {}", instr2);
16}
More examples
Hide additional examples
examples/all-u32.rs (line 10)
4fn main() {
5    let mut valid: u32 = 0;
6    for x in 0..u32::MAX {
7        if x % 10000 == 0 {
8            println!("{:.4}%", 100.0 * (x as f64) / (u32::MAX as f64))
9        }
10        if let Ok(i) = Instruction::decode(x) {
11            valid += 1;
12            let e = Instruction::encode(&i);
13            if x != e {
14                println!("i: {i}\nx: {x:032b}\ne: {e:032b}");
15                exit(1);
16            }
17
18            let d = i.to_string();
19            let i2 = assemble_line(&d).unwrap().i();
20            if i != i2 {
21                println!("disassembled {i:#?} to get {d}. Assembled to get {i2:#?}!");
22                exit(1);
23            }
24        }
25    }
26    println!("Done.");
27    println!("proportion of encoding space used: {}%", 100.0 * (valid as f64) / (u32::MAX as f64))
28}
Source

pub fn encode(instruction: &Instruction) -> u32

Examples found in repository?
examples/simple.rs (line 12)
2fn main() {
3    // instruction can be assembled from strings
4    let instr: Instruction = assemble_line("addi t0, t1, 1024").unwrap().i();
5    // and disassembled
6    println!("assembled instruction: {}", instr);
7
8    // instructions can also be decoded from binary
9    let instr2 = Instruction::decode(0xe0058513).unwrap();
10
11    // and encoded
12    assert_eq!(Instruction::encode(&instr2), 0xe0058513);
13
14    let instr2 = assemble_line("fcvt.lu.s zero,ft0,rne").unwrap().i();
15    println!("assembled instruction: {}", instr2);
16}
More examples
Hide additional examples
examples/all-u32.rs (line 12)
4fn main() {
5    let mut valid: u32 = 0;
6    for x in 0..u32::MAX {
7        if x % 10000 == 0 {
8            println!("{:.4}%", 100.0 * (x as f64) / (u32::MAX as f64))
9        }
10        if let Ok(i) = Instruction::decode(x) {
11            valid += 1;
12            let e = Instruction::encode(&i);
13            if x != e {
14                println!("i: {i}\nx: {x:032b}\ne: {e:032b}");
15                exit(1);
16            }
17
18            let d = i.to_string();
19            let i2 = assemble_line(&d).unwrap().i();
20            if i != i2 {
21                println!("disassembled {i:#?} to get {d}. Assembled to get {i2:#?}!");
22                exit(1);
23            }
24        }
25    }
26    println!("Done.");
27    println!("proportion of encoding space used: {}%", 100.0 * (valid as f64) / (u32::MAX as f64))
28}

Trait Implementations§

Source§

impl Debug for Instruction

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
Source§

impl Display for Instruction

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more
Source§

impl PartialEq for Instruction

Source§

fn eq(&self, other: &Instruction) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
Source§

impl StructuralPartialEq for Instruction

Auto Trait Implementations§

Blanket Implementations§

Source§

impl<T> Any for T
where T: 'static + ?Sized,

Source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> ToString for T
where T: Display + ?Sized,

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fn to_string(&self) -> String

Converts the given value to a String. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.