Struct cudaDeviceProp

Source
#[repr(C)]
pub struct cudaDeviceProp {
Show 80 fields pub name: [i8; 256], pub uuid: CUuuid_st, pub luid: [i8; 8], pub luidDeviceNodeMask: u32, pub totalGlobalMem: usize, pub sharedMemPerBlock: usize, pub regsPerBlock: i32, pub warpSize: i32, pub memPitch: usize, pub maxThreadsPerBlock: i32, pub maxThreadsDim: [i32; 3], pub maxGridSize: [i32; 3], pub clockRate: i32, pub totalConstMem: usize, pub major: i32, pub minor: i32, pub textureAlignment: usize, pub texturePitchAlignment: usize, pub deviceOverlap: i32, pub multiProcessorCount: i32, pub kernelExecTimeoutEnabled: i32, pub integrated: i32, pub canMapHostMemory: i32, pub computeMode: i32, pub maxTexture1D: i32, pub maxTexture1DMipmap: i32, pub maxTexture1DLinear: i32, pub maxTexture2D: [i32; 2], pub maxTexture2DMipmap: [i32; 2], pub maxTexture2DLinear: [i32; 3], pub maxTexture2DGather: [i32; 2], pub maxTexture3D: [i32; 3], pub maxTexture3DAlt: [i32; 3], pub maxTextureCubemap: i32, pub maxTexture1DLayered: [i32; 2], pub maxTexture2DLayered: [i32; 3], pub maxTextureCubemapLayered: [i32; 2], pub maxSurface1D: i32, pub maxSurface2D: [i32; 2], pub maxSurface3D: [i32; 3], pub maxSurface1DLayered: [i32; 2], pub maxSurface2DLayered: [i32; 3], pub maxSurfaceCubemap: i32, pub maxSurfaceCubemapLayered: [i32; 2], pub surfaceAlignment: usize, pub concurrentKernels: i32, pub ECCEnabled: i32, pub pciBusID: i32, pub pciDeviceID: i32, pub pciDomainID: i32, pub tccDriver: i32, pub asyncEngineCount: i32, pub unifiedAddressing: i32, pub memoryClockRate: i32, pub memoryBusWidth: i32, pub l2CacheSize: i32, pub persistingL2CacheMaxSize: i32, pub maxThreadsPerMultiProcessor: i32, pub streamPrioritiesSupported: i32, pub globalL1CacheSupported: i32, pub localL1CacheSupported: i32, pub sharedMemPerMultiprocessor: usize, pub regsPerMultiprocessor: i32, pub managedMemory: i32, pub isMultiGpuBoard: i32, pub multiGpuBoardGroupID: i32, pub hostNativeAtomicSupported: i32, pub singleToDoublePrecisionPerfRatio: i32, pub pageableMemoryAccess: i32, pub concurrentManagedAccess: i32, pub computePreemptionSupported: i32, pub canUseHostPointerForRegisteredMem: i32, pub cooperativeLaunch: i32, pub cooperativeMultiDeviceLaunch: i32, pub sharedMemPerBlockOptin: usize, pub pageableMemoryAccessUsesHostPageTables: i32, pub directManagedMemAccessFromHost: i32, pub maxBlocksPerMultiProcessor: i32, pub accessPolicyMaxWindowSize: i32, pub reservedSharedMemPerBlock: usize,
}
Expand description

CUDA device properties

Fields§

§name: [i8; 256]

< ASCII string identifying device

§uuid: CUuuid_st

< 16-byte unique identifier

§luid: [i8; 8]

< 8-byte locally unique identifier. Value is undefined on TCC and non-Windows platforms

§luidDeviceNodeMask: u32

< LUID device node mask. Value is undefined on TCC and non-Windows platforms

§totalGlobalMem: usize

< Global memory available on device in bytes

§sharedMemPerBlock: usize

< Shared memory available per block in bytes

§regsPerBlock: i32

< 32-bit registers available per block

§warpSize: i32

< Warp size in threads

§memPitch: usize

< Maximum pitch in bytes allowed by memory copies

§maxThreadsPerBlock: i32

< Maximum number of threads per block

§maxThreadsDim: [i32; 3]

< Maximum size of each dimension of a block

§maxGridSize: [i32; 3]

< Maximum size of each dimension of a grid

§clockRate: i32

< Clock frequency in kilohertz

§totalConstMem: usize

< Constant memory available on device in bytes

§major: i32

< Major compute capability

§minor: i32

< Minor compute capability

§textureAlignment: usize

< Alignment requirement for textures

§texturePitchAlignment: usize

< Pitch alignment requirement for texture references bound to pitched memory

§deviceOverlap: i32

< Device can concurrently copy memory and execute a kernel. Deprecated. Use instead asyncEngineCount.

§multiProcessorCount: i32

< Number of multiprocessors on device

§kernelExecTimeoutEnabled: i32

< Specified whether there is a run time limit on kernels

§integrated: i32

< Device is integrated as opposed to discrete

§canMapHostMemory: i32

< Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer

§computeMode: i32

< Compute mode (See ::cudaComputeMode)

§maxTexture1D: i32

< Maximum 1D texture size

§maxTexture1DMipmap: i32

< Maximum 1D mipmapped texture size

§maxTexture1DLinear: i32

< Deprecated, do not use. Use cudaDeviceGetTexture1DLinearMaxWidth() or cuDeviceGetTexture1DLinearMaxWidth() instead.

§maxTexture2D: [i32; 2]

< Maximum 2D texture dimensions

§maxTexture2DMipmap: [i32; 2]

< Maximum 2D mipmapped texture dimensions

§maxTexture2DLinear: [i32; 3]

< Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory

§maxTexture2DGather: [i32; 2]

< Maximum 2D texture dimensions if texture gather operations have to be performed

§maxTexture3D: [i32; 3]

< Maximum 3D texture dimensions

§maxTexture3DAlt: [i32; 3]

< Maximum alternate 3D texture dimensions

§maxTextureCubemap: i32

< Maximum Cubemap texture dimensions

§maxTexture1DLayered: [i32; 2]

< Maximum 1D layered texture dimensions

§maxTexture2DLayered: [i32; 3]

< Maximum 2D layered texture dimensions

§maxTextureCubemapLayered: [i32; 2]

< Maximum Cubemap layered texture dimensions

§maxSurface1D: i32

< Maximum 1D surface size

§maxSurface2D: [i32; 2]

< Maximum 2D surface dimensions

§maxSurface3D: [i32; 3]

< Maximum 3D surface dimensions

§maxSurface1DLayered: [i32; 2]

< Maximum 1D layered surface dimensions

§maxSurface2DLayered: [i32; 3]

< Maximum 2D layered surface dimensions

§maxSurfaceCubemap: i32

< Maximum Cubemap surface dimensions

§maxSurfaceCubemapLayered: [i32; 2]

< Maximum Cubemap layered surface dimensions

§surfaceAlignment: usize

< Alignment requirements for surfaces

§concurrentKernels: i32

< Device can possibly execute multiple kernels concurrently

§ECCEnabled: i32

< Device has ECC support enabled

§pciBusID: i32

< PCI bus ID of the device

§pciDeviceID: i32

< PCI device ID of the device

§pciDomainID: i32

< PCI domain ID of the device

§tccDriver: i32

< 1 if device is a Tesla device using TCC driver, 0 otherwise

§asyncEngineCount: i32

< Number of asynchronous engines

§unifiedAddressing: i32

< Device shares a unified address space with the host

§memoryClockRate: i32

< Peak memory clock frequency in kilohertz

§memoryBusWidth: i32

< Global memory bus width in bits

§l2CacheSize: i32

< Size of L2 cache in bytes

§persistingL2CacheMaxSize: i32

< Device’s maximum l2 persisting lines capacity setting in bytes

§maxThreadsPerMultiProcessor: i32

< Maximum resident threads per multiprocessor

§streamPrioritiesSupported: i32

< Device supports stream priorities

§globalL1CacheSupported: i32

< Device supports caching globals in L1

§localL1CacheSupported: i32

< Device supports caching locals in L1

§sharedMemPerMultiprocessor: usize

< Shared memory available per multiprocessor in bytes

§regsPerMultiprocessor: i32

< 32-bit registers available per multiprocessor

§managedMemory: i32

< Device supports allocating managed memory on this system

§isMultiGpuBoard: i32

< Device is on a multi-GPU board

§multiGpuBoardGroupID: i32

< Unique identifier for a group of devices on the same multi-GPU board

§hostNativeAtomicSupported: i32

< Link between the device and the host supports native atomic operations

§singleToDoublePrecisionPerfRatio: i32

< Ratio of single precision performance (in floating-point operations per second) to double precision performance

§pageableMemoryAccess: i32

< Device supports coherently accessing pageable memory without calling cudaHostRegister on it

§concurrentManagedAccess: i32

< Device can coherently access managed memory concurrently with the CPU

§computePreemptionSupported: i32

< Device supports Compute Preemption

§canUseHostPointerForRegisteredMem: i32

< Device can access host registered memory at the same virtual address as the CPU

§cooperativeLaunch: i32

< Device supports launching cooperative kernels via ::cudaLaunchCooperativeKernel

§cooperativeMultiDeviceLaunch: i32

< Deprecated, cudaLaunchCooperativeKernelMultiDevice is deprecated.

§sharedMemPerBlockOptin: usize

< Per device maximum shared memory per block usable by special opt in

§pageableMemoryAccessUsesHostPageTables: i32

< Device accesses pageable memory via the host’s page tables

§directManagedMemAccessFromHost: i32

< Host can directly access managed memory on the device without migration.

§maxBlocksPerMultiProcessor: i32

< Maximum number of resident blocks per multiprocessor

§accessPolicyMaxWindowSize: i32

< The maximum value of ::cudaAccessPolicyWindow::num_bytes.

§reservedSharedMemPerBlock: usize

< Shared memory reserved by CUDA driver per block in bytes

Trait Implementations§

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impl Clone for cudaDeviceProp

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fn clone(&self) -> cudaDeviceProp

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Copy for cudaDeviceProp

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unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
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Calls U::from(self).

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