#[non_exhaustive]#[repr(u32)]pub enum cudaDeviceAttr {
Show 113 variants
cudaDevAttrMaxThreadsPerBlock = 1,
cudaDevAttrMaxBlockDimX = 2,
cudaDevAttrMaxBlockDimY = 3,
cudaDevAttrMaxBlockDimZ = 4,
cudaDevAttrMaxGridDimX = 5,
cudaDevAttrMaxGridDimY = 6,
cudaDevAttrMaxGridDimZ = 7,
cudaDevAttrMaxSharedMemoryPerBlock = 8,
cudaDevAttrTotalConstantMemory = 9,
cudaDevAttrWarpSize = 10,
cudaDevAttrMaxPitch = 11,
cudaDevAttrMaxRegistersPerBlock = 12,
cudaDevAttrClockRate = 13,
cudaDevAttrTextureAlignment = 14,
cudaDevAttrGpuOverlap = 15,
cudaDevAttrMultiProcessorCount = 16,
cudaDevAttrKernelExecTimeout = 17,
cudaDevAttrIntegrated = 18,
cudaDevAttrCanMapHostMemory = 19,
cudaDevAttrComputeMode = 20,
cudaDevAttrMaxTexture1DWidth = 21,
cudaDevAttrMaxTexture2DWidth = 22,
cudaDevAttrMaxTexture2DHeight = 23,
cudaDevAttrMaxTexture3DWidth = 24,
cudaDevAttrMaxTexture3DHeight = 25,
cudaDevAttrMaxTexture3DDepth = 26,
cudaDevAttrMaxTexture2DLayeredWidth = 27,
cudaDevAttrMaxTexture2DLayeredHeight = 28,
cudaDevAttrMaxTexture2DLayeredLayers = 29,
cudaDevAttrSurfaceAlignment = 30,
cudaDevAttrConcurrentKernels = 31,
cudaDevAttrEccEnabled = 32,
cudaDevAttrPciBusId = 33,
cudaDevAttrPciDeviceId = 34,
cudaDevAttrTccDriver = 35,
cudaDevAttrMemoryClockRate = 36,
cudaDevAttrGlobalMemoryBusWidth = 37,
cudaDevAttrL2CacheSize = 38,
cudaDevAttrMaxThreadsPerMultiProcessor = 39,
cudaDevAttrAsyncEngineCount = 40,
cudaDevAttrUnifiedAddressing = 41,
cudaDevAttrMaxTexture1DLayeredWidth = 42,
cudaDevAttrMaxTexture1DLayeredLayers = 43,
cudaDevAttrMaxTexture2DGatherWidth = 45,
cudaDevAttrMaxTexture2DGatherHeight = 46,
cudaDevAttrMaxTexture3DWidthAlt = 47,
cudaDevAttrMaxTexture3DHeightAlt = 48,
cudaDevAttrMaxTexture3DDepthAlt = 49,
cudaDevAttrPciDomainId = 50,
cudaDevAttrTexturePitchAlignment = 51,
cudaDevAttrMaxTextureCubemapWidth = 52,
cudaDevAttrMaxTextureCubemapLayeredWidth = 53,
cudaDevAttrMaxTextureCubemapLayeredLayers = 54,
cudaDevAttrMaxSurface1DWidth = 55,
cudaDevAttrMaxSurface2DWidth = 56,
cudaDevAttrMaxSurface2DHeight = 57,
cudaDevAttrMaxSurface3DWidth = 58,
cudaDevAttrMaxSurface3DHeight = 59,
cudaDevAttrMaxSurface3DDepth = 60,
cudaDevAttrMaxSurface1DLayeredWidth = 61,
cudaDevAttrMaxSurface1DLayeredLayers = 62,
cudaDevAttrMaxSurface2DLayeredWidth = 63,
cudaDevAttrMaxSurface2DLayeredHeight = 64,
cudaDevAttrMaxSurface2DLayeredLayers = 65,
cudaDevAttrMaxSurfaceCubemapWidth = 66,
cudaDevAttrMaxSurfaceCubemapLayeredWidth = 67,
cudaDevAttrMaxSurfaceCubemapLayeredLayers = 68,
cudaDevAttrMaxTexture1DLinearWidth = 69,
cudaDevAttrMaxTexture2DLinearWidth = 70,
cudaDevAttrMaxTexture2DLinearHeight = 71,
cudaDevAttrMaxTexture2DLinearPitch = 72,
cudaDevAttrMaxTexture2DMipmappedWidth = 73,
cudaDevAttrMaxTexture2DMipmappedHeight = 74,
cudaDevAttrComputeCapabilityMajor = 75,
cudaDevAttrComputeCapabilityMinor = 76,
cudaDevAttrMaxTexture1DMipmappedWidth = 77,
cudaDevAttrStreamPrioritiesSupported = 78,
cudaDevAttrGlobalL1CacheSupported = 79,
cudaDevAttrLocalL1CacheSupported = 80,
cudaDevAttrMaxSharedMemoryPerMultiprocessor = 81,
cudaDevAttrMaxRegistersPerMultiprocessor = 82,
cudaDevAttrManagedMemory = 83,
cudaDevAttrIsMultiGpuBoard = 84,
cudaDevAttrMultiGpuBoardGroupID = 85,
cudaDevAttrHostNativeAtomicSupported = 86,
cudaDevAttrSingleToDoublePrecisionPerfRatio = 87,
cudaDevAttrPageableMemoryAccess = 88,
cudaDevAttrConcurrentManagedAccess = 89,
cudaDevAttrComputePreemptionSupported = 90,
cudaDevAttrCanUseHostPointerForRegisteredMem = 91,
cudaDevAttrReserved92 = 92,
cudaDevAttrReserved93 = 93,
cudaDevAttrReserved94 = 94,
cudaDevAttrCooperativeLaunch = 95,
cudaDevAttrCooperativeMultiDeviceLaunch = 96,
cudaDevAttrMaxSharedMemoryPerBlockOptin = 97,
cudaDevAttrCanFlushRemoteWrites = 98,
cudaDevAttrHostRegisterSupported = 99,
cudaDevAttrPageableMemoryAccessUsesHostPageTables = 100,
cudaDevAttrDirectManagedMemAccessFromHost = 101,
cudaDevAttrMaxBlocksPerMultiprocessor = 106,
cudaDevAttrMaxPersistingL2CacheSize = 108,
cudaDevAttrMaxAccessPolicyWindowSize = 109,
cudaDevAttrReservedSharedMemoryPerBlock = 111,
cudaDevAttrSparseCudaArraySupported = 112,
cudaDevAttrHostRegisterReadOnlySupported = 113,
cudaDevAttrMaxTimelineSemaphoreInteropSupported = 114,
cudaDevAttrMemoryPoolsSupported = 115,
cudaDevAttrGPUDirectRDMASupported = 116,
cudaDevAttrGPUDirectRDMAFlushWritesOptions = 117,
cudaDevAttrGPUDirectRDMAWritesOrdering = 118,
cudaDevAttrMemoryPoolSupportedHandleTypes = 119,
cudaDevAttrMax = 120,
}Expand description
CUDA device attributes
Variants (Non-exhaustive)§
This enum is marked as non-exhaustive
cudaDevAttrMaxThreadsPerBlock = 1
< Maximum number of threads per block
cudaDevAttrMaxBlockDimX = 2
< Maximum block dimension X
cudaDevAttrMaxBlockDimY = 3
< Maximum block dimension Y
cudaDevAttrMaxBlockDimZ = 4
< Maximum block dimension Z
cudaDevAttrMaxGridDimX = 5
< Maximum grid dimension X
cudaDevAttrMaxGridDimY = 6
< Maximum grid dimension Y
cudaDevAttrMaxGridDimZ = 7
< Maximum grid dimension Z
< Maximum shared memory available per block in bytes
cudaDevAttrTotalConstantMemory = 9
< Memory available on device for constant variables in a CUDA C kernel in bytes
cudaDevAttrWarpSize = 10
< Warp size in threads
cudaDevAttrMaxPitch = 11
< Maximum pitch in bytes allowed by memory copies
cudaDevAttrMaxRegistersPerBlock = 12
< Maximum number of 32-bit registers available per block
cudaDevAttrClockRate = 13
< Peak clock frequency in kilohertz
cudaDevAttrTextureAlignment = 14
< Alignment requirement for textures
cudaDevAttrGpuOverlap = 15
< Device can possibly copy memory and execute a kernel concurrently
cudaDevAttrMultiProcessorCount = 16
< Number of multiprocessors on device
cudaDevAttrKernelExecTimeout = 17
< Specifies whether there is a run time limit on kernels
cudaDevAttrIntegrated = 18
< Device is integrated with host memory
cudaDevAttrCanMapHostMemory = 19
< Device can map host memory into CUDA address space
cudaDevAttrComputeMode = 20
< Compute mode (See ::cudaComputeMode for details)
cudaDevAttrMaxTexture1DWidth = 21
< Maximum 1D texture width
cudaDevAttrMaxTexture2DWidth = 22
< Maximum 2D texture width
cudaDevAttrMaxTexture2DHeight = 23
< Maximum 2D texture height
cudaDevAttrMaxTexture3DWidth = 24
< Maximum 3D texture width
cudaDevAttrMaxTexture3DHeight = 25
< Maximum 3D texture height
cudaDevAttrMaxTexture3DDepth = 26
< Maximum 3D texture depth
cudaDevAttrMaxTexture2DLayeredWidth = 27
< Maximum 2D layered texture width
cudaDevAttrMaxTexture2DLayeredHeight = 28
< Maximum 2D layered texture height
cudaDevAttrMaxTexture2DLayeredLayers = 29
< Maximum layers in a 2D layered texture
cudaDevAttrSurfaceAlignment = 30
< Alignment requirement for surfaces
cudaDevAttrConcurrentKernels = 31
< Device can possibly execute multiple kernels concurrently
cudaDevAttrEccEnabled = 32
< Device has ECC support enabled
cudaDevAttrPciBusId = 33
< PCI bus ID of the device
cudaDevAttrPciDeviceId = 34
< PCI device ID of the device
cudaDevAttrTccDriver = 35
< Device is using TCC driver model
cudaDevAttrMemoryClockRate = 36
< Peak memory clock frequency in kilohertz
cudaDevAttrGlobalMemoryBusWidth = 37
< Global memory bus width in bits
cudaDevAttrL2CacheSize = 38
< Size of L2 cache in bytes
cudaDevAttrMaxThreadsPerMultiProcessor = 39
< Maximum resident threads per multiprocessor
cudaDevAttrAsyncEngineCount = 40
< Number of asynchronous engines
cudaDevAttrUnifiedAddressing = 41
< Device shares a unified address space with the host
cudaDevAttrMaxTexture1DLayeredWidth = 42
< Maximum 1D layered texture width
cudaDevAttrMaxTexture1DLayeredLayers = 43
< Maximum layers in a 1D layered texture
cudaDevAttrMaxTexture2DGatherWidth = 45
< Maximum 2D texture width if cudaArrayTextureGather is set
cudaDevAttrMaxTexture2DGatherHeight = 46
< Maximum 2D texture height if cudaArrayTextureGather is set
cudaDevAttrMaxTexture3DWidthAlt = 47
< Alternate maximum 3D texture width
cudaDevAttrMaxTexture3DHeightAlt = 48
< Alternate maximum 3D texture height
cudaDevAttrMaxTexture3DDepthAlt = 49
< Alternate maximum 3D texture depth
cudaDevAttrPciDomainId = 50
< PCI domain ID of the device
cudaDevAttrTexturePitchAlignment = 51
< Pitch alignment requirement for textures
cudaDevAttrMaxTextureCubemapWidth = 52
< Maximum cubemap texture width/height
cudaDevAttrMaxTextureCubemapLayeredWidth = 53
< Maximum cubemap layered texture width/height
cudaDevAttrMaxTextureCubemapLayeredLayers = 54
< Maximum layers in a cubemap layered texture
cudaDevAttrMaxSurface1DWidth = 55
< Maximum 1D surface width
cudaDevAttrMaxSurface2DWidth = 56
< Maximum 2D surface width
cudaDevAttrMaxSurface2DHeight = 57
< Maximum 2D surface height
cudaDevAttrMaxSurface3DWidth = 58
< Maximum 3D surface width
cudaDevAttrMaxSurface3DHeight = 59
< Maximum 3D surface height
cudaDevAttrMaxSurface3DDepth = 60
< Maximum 3D surface depth
cudaDevAttrMaxSurface1DLayeredWidth = 61
< Maximum 1D layered surface width
cudaDevAttrMaxSurface1DLayeredLayers = 62
< Maximum layers in a 1D layered surface
cudaDevAttrMaxSurface2DLayeredWidth = 63
< Maximum 2D layered surface width
cudaDevAttrMaxSurface2DLayeredHeight = 64
< Maximum 2D layered surface height
cudaDevAttrMaxSurface2DLayeredLayers = 65
< Maximum layers in a 2D layered surface
cudaDevAttrMaxSurfaceCubemapWidth = 66
< Maximum cubemap surface width
cudaDevAttrMaxSurfaceCubemapLayeredWidth = 67
< Maximum cubemap layered surface width
cudaDevAttrMaxSurfaceCubemapLayeredLayers = 68
< Maximum layers in a cubemap layered surface
cudaDevAttrMaxTexture1DLinearWidth = 69
< Maximum 1D linear texture width
cudaDevAttrMaxTexture2DLinearWidth = 70
< Maximum 2D linear texture width
cudaDevAttrMaxTexture2DLinearHeight = 71
< Maximum 2D linear texture height
cudaDevAttrMaxTexture2DLinearPitch = 72
< Maximum 2D linear texture pitch in bytes
cudaDevAttrMaxTexture2DMipmappedWidth = 73
< Maximum mipmapped 2D texture width
cudaDevAttrMaxTexture2DMipmappedHeight = 74
< Maximum mipmapped 2D texture height
cudaDevAttrComputeCapabilityMajor = 75
< Major compute capability version number
cudaDevAttrComputeCapabilityMinor = 76
< Minor compute capability version number
cudaDevAttrMaxTexture1DMipmappedWidth = 77
< Maximum mipmapped 1D texture width
cudaDevAttrStreamPrioritiesSupported = 78
< Device supports stream priorities
cudaDevAttrGlobalL1CacheSupported = 79
< Device supports caching globals in L1
cudaDevAttrLocalL1CacheSupported = 80
< Device supports caching locals in L1
< Maximum shared memory available per multiprocessor in bytes
cudaDevAttrMaxRegistersPerMultiprocessor = 82
< Maximum number of 32-bit registers available per multiprocessor
cudaDevAttrManagedMemory = 83
< Device can allocate managed memory on this system
cudaDevAttrIsMultiGpuBoard = 84
< Device is on a multi-GPU board
cudaDevAttrMultiGpuBoardGroupID = 85
< Unique identifier for a group of devices on the same multi-GPU board
cudaDevAttrHostNativeAtomicSupported = 86
< Link between the device and the host supports native atomic operations
cudaDevAttrSingleToDoublePrecisionPerfRatio = 87
< Ratio of single precision performance (in floating-point operations per second) to double precision performance
cudaDevAttrPageableMemoryAccess = 88
< Device supports coherently accessing pageable memory without calling cudaHostRegister on it
cudaDevAttrConcurrentManagedAccess = 89
< Device can coherently access managed memory concurrently with the CPU
cudaDevAttrComputePreemptionSupported = 90
< Device supports Compute Preemption
cudaDevAttrCanUseHostPointerForRegisteredMem = 91
< Device can access host registered memory at the same virtual address as the CPU
cudaDevAttrReserved92 = 92
cudaDevAttrReserved93 = 93
cudaDevAttrReserved94 = 94
cudaDevAttrCooperativeLaunch = 95
< Device supports launching cooperative kernels via ::cudaLaunchCooperativeKernel
cudaDevAttrCooperativeMultiDeviceLaunch = 96
< Deprecated, cudaLaunchCooperativeKernelMultiDevice is deprecated.
< The maximum optin shared memory per block. This value may vary by chip. See ::cudaFuncSetAttribute
cudaDevAttrCanFlushRemoteWrites = 98
< Device supports flushing of outstanding remote writes.
cudaDevAttrHostRegisterSupported = 99
< Device supports host memory registration via ::cudaHostRegister.
cudaDevAttrPageableMemoryAccessUsesHostPageTables = 100
< Device accesses pageable memory via the host’s page tables.
cudaDevAttrDirectManagedMemAccessFromHost = 101
< Host can directly access managed memory on the device without migration.
cudaDevAttrMaxBlocksPerMultiprocessor = 106
< Maximum number of blocks per multiprocessor
cudaDevAttrMaxPersistingL2CacheSize = 108
< Maximum L2 persisting lines capacity setting in bytes.
cudaDevAttrMaxAccessPolicyWindowSize = 109
< Maximum value of cudaAccessPolicyWindow::num_bytes.
< Shared memory reserved by CUDA driver per block in bytes
cudaDevAttrSparseCudaArraySupported = 112
< Device supports sparse CUDA arrays and sparse CUDA mipmapped arrays
cudaDevAttrHostRegisterReadOnlySupported = 113
< Device supports using the ::cudaHostRegister flag cudaHostRegisterReadOnly to register memory that must be mapped as read-only to the GPU
cudaDevAttrMaxTimelineSemaphoreInteropSupported = 114
< External timeline semaphore interop is supported on the device
cudaDevAttrMemoryPoolsSupported = 115
< Device supports using the ::cudaMallocAsync and ::cudaMemPool family of APIs
cudaDevAttrGPUDirectRDMASupported = 116
< Device supports GPUDirect RDMA APIs, like nvidia_p2p_get_pages (see https://docs.nvidia.com/cuda/gpudirect-rdma for more information)
cudaDevAttrGPUDirectRDMAFlushWritesOptions = 117
< The returned attribute shall be interpreted as a bitmask, where the individual bits are listed in the ::cudaFlushGPUDirectRDMAWritesOptions enum
cudaDevAttrGPUDirectRDMAWritesOrdering = 118
< GPUDirect RDMA writes to the device do not need to be flushed for consumers within the scope indicated by the returned attribute. See ::cudaGPUDirectRDMAWritesOrdering for the numerical values returned here.
cudaDevAttrMemoryPoolSupportedHandleTypes = 119
< Handle types supported with mempool based IPC
cudaDevAttrMax = 120
Trait Implementations§
Source§impl Clone for cudaDeviceAttr
impl Clone for cudaDeviceAttr
Source§fn clone(&self) -> cudaDeviceAttr
fn clone(&self) -> cudaDeviceAttr
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more