Struct raw_cpuid::ProcessorTraceInfo
[−]
[src]
pub struct ProcessorTraceInfo {
// some fields omitted
}Methods
impl ProcessorTraceInfo[src]
fn has_rtit_cr3_match(&self) -> bool
If true, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH MSR can be accessed.
fn has_configurable_psb_and_cycle_accurate_mode(&self) -> bool
If true, Indicates support of Configurable PSB and Cycle-Accurate Mode.
fn has_ip_tracestop_filtering(&self) -> bool
If true, Indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across warm reset.
fn has_mtc_timing_packet_coefi_suppression(&self) -> bool
If true, Indicates support of MTC timing packet and suppression of COFI-based packets.
fn has_topa(&self) -> bool
If true, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
fn has_topa_maximum_entries(&self) -> bool
If true, ToPA tables can hold any number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.
fn has_single_range_output_scheme(&self) -> bool
If true, Indicates support of Single-Range Output scheme.
fn has_trace_transport_subsystem(&self) -> bool
If true, Indicates support of output to Trace Transport subsystem.
fn has_lip_with_cs_base(&self) -> bool
If true, Generated packets which contain IP payloads have LIP values, which include the CS base component.
fn iter(&self) -> ProcessorTraceIter
Iterator over processor trace info sub-leafs.