Struct Controller

pub struct Controller<T: DramSpec> {

    pub channel: Dram<T>,
    pub scheduler: Scheduler,
    pub row_policy: RowPolicy,
    pub row_table: RowTable,
    pub refresh: Refresh,
    pub read_queue: Queue,
    pub write_queue: Queue,
    pub act_queue: Queue,
    pub other_queue: Queue,
    pub pending_queue: VecDeque<Request>,
    pub finished_queue: VecDeque<Request>,
    pub running_mode: RunningMode,
    pub wr_hight_watermark: f32,
    pub wr_low_watermark: f32,
}

Fields

channel: Dram<T>

scheduler: Scheduler

row_policy: RowPolicy

row_table: RowTable

refresh: Refresh

read_queue: Queue

write_queue: Queue

act_queue: Queue

other_queue: Queue

pending_queue: VecDeque<Request>

finished_queue: VecDeque<Request>

running_mode: RunningMode

wr_hight_watermark: f32

wr_low_watermark: f32

Implementations

impl<T> Controller<T>

where T: DramSpec,

pub fn new(_config: &Config, dram: Dram<T>) -> Self

pub fn finish(_read_req: u64, _dram_cycles: u64)

pub fn try_enqueue(&mut self, req: Request) -> Result<(), Request>

pub fn tick(&mut self, spec: &T, clk: u64)

pub fn is_ready_req(&self, _cmd: &Request) -> bool

pub fn is_ready_cmd( &self, spec: &T, cmd: &T::Command, addr_vec: &[u64], clk: u64, ) -> bool

pub fn is_row_hit_req(&self, _req: &Request) -> bool

pub fn is_row_hit_cmd(&self, _cmd: &T::Command, _addr_vec: &[u64]) -> bool

pub fn is_row_open_req(&self, _req: &Request) -> bool

pub fn is_row_open_cmd(&self, _cmd: &T::Command, _addr_vec: &[u64]) -> bool

pub fn is_active(&self) -> bool

pub fn is_refreshing(&self) -> bool