Struct BusNs 

pub struct BusNs { /* private fields */ }

Implementations

impl BusNs

pub const fn csmod( &self, ) -> &'static ClusterRegisterArray<Reg<Csmod_SPEC, RW>, 8, 0x10>

CS%s Mode Register (n = 0 to 7)

pub const fn cs0mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs1mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs2mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs3mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs4mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs5mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs6mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cs7mod(&self) -> &'static Reg<Csmod_SPEC, RW>

pub const fn cswcr1( &self, ) -> &'static ClusterRegisterArray<Reg<Cswcr1_SPEC, RW>, 8, 0x10>

CS%s Wait Control Register 1 (n = 0 to 7)

pub const fn cs0wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs1wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs2wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs3wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs4wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs5wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs6wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cs7wcr1(&self) -> &'static Reg<Cswcr1_SPEC, RW>

pub const fn cswcr2( &self, ) -> &'static ClusterRegisterArray<Reg<Cswcr2_SPEC, RW>, 8, 0x10>

CS%s Wait Control Register 2 (n = 0 to 7)

pub const fn cs0wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs1wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs2wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs3wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs4wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs5wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs6wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs7wcr2(&self) -> &'static Reg<Cswcr2_SPEC, RW>

pub const fn cs0cr(&self) -> &'static Reg<Cs0Cr_SPEC, RW>

CS0 Control Register

pub const fn csrec( &self, ) -> &'static ClusterRegisterArray<Reg<Csrec_SPEC, RW>, 8, 0x10>

CS%s Recovery Cycle Register (n = 0 to 7)

pub const fn cs0rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs1rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs2rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs3rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs4rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs5rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs6rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cs7rec(&self) -> &'static Reg<Csrec_SPEC, RW>

pub const fn cscr( &self, ) -> &'static ClusterRegisterArray<Reg<Cscr_SPEC, RW>, 7, 0x10>

CS%s Control Register

pub const fn cs1cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn cs2cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn cs3cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn cs4cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn cs5cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn cs6cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn cs7cr(&self) -> &'static Reg<Cscr_SPEC, RW>

pub const fn csrecen(&self) -> &'static Reg<Csrecen_SPEC, RW>

CS Recovery Cycle Insertion Enable Register

pub const fn sdccr(&self) -> &'static Reg<Sdccr_SPEC, RW>

SDC Control Register

pub const fn sdcmod(&self) -> &'static Reg<Sdcmod_SPEC, RW>

SDC Mode Register

pub const fn sdamod(&self) -> &'static Reg<Sdamod_SPEC, RW>

SDRAM Access Mode Register

pub const fn sdself(&self) -> &'static Reg<Sdself_SPEC, RW>

SDRAM Self-Refresh Control Register

pub const fn sdrfcr(&self) -> &'static Reg<Sdrfcr_SPEC, RW>

SDRAM Refresh Control Register

pub const fn sdrfen(&self) -> &'static Reg<Sdrfen_SPEC, RW>

SDRAM Auto-Refresh Control Register

pub const fn sdicr(&self) -> &'static Reg<Sdicr_SPEC, RW>

SDRAM Initialization Sequence Control Register

pub const fn sdir(&self) -> &'static Reg<Sdir_SPEC, RW>

SDRAM Initialization Register

pub const fn sdadr(&self) -> &'static Reg<Sdadr_SPEC, RW>

SDRAM Address Register

pub const fn sdtr(&self) -> &'static Reg<Sdtr_SPEC, RW>

SDRAM Timing Register

pub const fn sdmod(&self) -> &'static Reg<Sdmod_SPEC, RW>

SDRAM Mode Register

pub const fn sdsr(&self) -> &'static Reg<Sdsr_SPEC, R>

SDRAM Status Register

pub const fn busoad(&self) -> &'static Reg<Busoad_SPEC, RW>

BUS Operation After Detection Register

pub const fn busoadpt(&self) -> &'static Reg<Busoadpt_SPEC, RW>

BUS Operation After Detection Protect Register

pub const fn busmabt(&self) -> &'static Reg<Busmabt_SPEC, RW>

Bus Master Arbitration Control Register

pub const fn bussabt1fhbi(&self) -> &'static Reg<Bussabt1Fhbi_SPEC, RW>

Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)

pub const fn bussabt0flbi(&self) -> &'static Reg<Bussabt0Flbi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt1s0bi(&self) -> &'static Reg<Bussabt1S0Bi_SPEC, RW>

Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)

pub const fn bussabt1s1bi(&self) -> &'static Reg<Bussabt1S1Bi_SPEC, RW>

Bus Slave Arbitration Control Register 1(x = FHBI, S0BI, S1BI)

pub const fn bussabt0stbysbi(&self) -> &'static Reg<Bussabt0Stbysbi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt0ecbi(&self) -> &'static Reg<Bussabt0Ecbi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt0eobi(&self) -> &'static Reg<Bussabt0Eobi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt0pbbi(&self) -> &'static Reg<Bussabt0Pbbi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt0pabi(&self) -> &'static Reg<Bussabt0Pabi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt0pibi(&self) -> &'static Reg<Bussabt0Pibi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn bussabt0psbi(&self) -> &'static Reg<Bussabt0Psbi_SPEC, RW>

Bus Slave Arbitration Control Register 0

pub const fn busdivbyp(&self) -> &'static Reg<Busdivbyp_SPEC, RW>

Bus Divider Bypass Register

pub const fn buserrrw( &self, ) -> &'static ClusterRegisterArray<Reg<Buserrrw_SPEC, R>, 4, 0x10>

BUS Error Read Write (n = 6 to 9)

pub const fn bus6errrw(&self) -> &'static Reg<Buserrrw_SPEC, R>

pub const fn bus7errrw(&self) -> &'static Reg<Buserrrw_SPEC, R>

pub const fn bus8errrw(&self) -> &'static Reg<Buserrrw_SPEC, R>

pub const fn bus9errrw(&self) -> &'static Reg<Buserrrw_SPEC, R>

pub const fn buserradd( &self, ) -> &'static ClusterRegisterArray<Reg<Buserradd_SPEC, R>, 4, 0x10>

BUS Error Address Register (n = 6 to 9)

pub const fn bus6erradd(&self) -> &'static Reg<Buserradd_SPEC, R>

pub const fn bus7erradd(&self) -> &'static Reg<Buserradd_SPEC, R>

pub const fn bus8erradd(&self) -> &'static Reg<Buserradd_SPEC, R>

pub const fn bus9erradd(&self) -> &'static Reg<Buserradd_SPEC, R>

pub const fn bmsaerradd( &self, ) -> &'static ClusterRegisterArray<Reg<Bmsaerradd_SPEC, R>, 4, 0x10>

Bus Master Security Attribution Unit Error Address

pub const fn bmsa6erradd(&self) -> &'static Reg<Bmsaerradd_SPEC, R>

pub const fn bmsa7erradd(&self) -> &'static Reg<Bmsaerradd_SPEC, R>

pub const fn bmsa8erradd(&self) -> &'static Reg<Bmsaerradd_SPEC, R>

pub const fn bmsa9erradd(&self) -> &'static Reg<Bmsaerradd_SPEC, R>

pub const fn bmsaerrrw( &self, ) -> &'static ClusterRegisterArray<Reg<Bmsaerrrw_SPEC, R>, 4, 0x10>

BUS Master Security Attribution Unit Error Read Write (n = 6 to 9)

pub const fn bmsa6errrw(&self) -> &'static Reg<Bmsaerrrw_SPEC, R>

pub const fn bmsa7errrw(&self) -> &'static Reg<Bmsaerrrw_SPEC, R>

pub const fn bmsa8errrw(&self) -> &'static Reg<Bmsaerrrw_SPEC, R>

pub const fn bmsa9errrw(&self) -> &'static Reg<Bmsaerrrw_SPEC, R>

pub const fn buserrstat( &self, ) -> &'static ClusterRegisterArray<Reg<Buserrstat_SPEC, R>, 4, 0x10>

BUS Error Status Register

pub const fn bus6errstat(&self) -> &'static Reg<Buserrstat_SPEC, R>

pub const fn bus7errstat(&self) -> &'static Reg<Buserrstat_SPEC, R>

pub const fn bus8errstat(&self) -> &'static Reg<Buserrstat_SPEC, R>

pub const fn bus9errstat(&self) -> &'static Reg<Buserrstat_SPEC, R>

pub const fn buserrclr( &self, ) -> &'static ClusterRegisterArray<Reg<Buserrclr_SPEC, RW>, 4, 0x10>

BUS Error Clear Register

pub const fn bus6errclr(&self) -> &'static Reg<Buserrclr_SPEC, RW>

pub const fn bus7errclr(&self) -> &'static Reg<Buserrclr_SPEC, RW>

pub const fn bus8errclr(&self) -> &'static Reg<Buserrclr_SPEC, RW>

pub const fn bus9errclr(&self) -> &'static Reg<Buserrclr_SPEC, RW>

pub const fn mbwerrstat(&self) -> &'static Reg<Mbwerrstat_SPEC, R>

Master Bufferable Write Error Status Register

pub const fn mbwerrclr(&self) -> &'static Reg<Mbwerrclr_SPEC, RW>

Master Bufferable Write Error Clear Register

pub const fn sbwerrstat(&self) -> &'static Reg<Sbwerrstat_SPEC, R>

Slave Bufferable Write Error Status Register

pub const fn sbwerrclr(&self) -> &'static Reg<Sbwerrclr_SPEC, RW>

Slave Bufferable Write Error Clear Register

Trait Implementations

impl Clone for BusNs

fn clone(&self) -> BusNs

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for BusNs

fn eq(&self, other: &BusNs) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for BusNs

impl Eq for BusNs

impl Send for BusNs

Bus Control

impl StructuralPartialEq for BusNs

impl Sync for BusNs