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RegisterBlock

ra6m3::glcdc

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 114 fields
    pub gr1_clut0: [GR1_CLUT0; 256],
    pub gr1_clut1: [GR1_CLUT1; 256],
    pub gr2_clut0: [GR2_CLUT0; 256],
    pub gr2_clut1: [GR2_CLUT1; 256],
    pub bg_en: BG_EN,
    pub bg_peri: BG_PERI,
    pub bg_sync: BG_SYNC,
    pub bg_vsize: BG_VSIZE,
    pub bg_hsize: BG_HSIZE,
    pub bg_bgc: BG_BGC,
    pub bg_mon: BG_MON,
    pub gr1_ven: GR_VEN,
    pub gr1_flmrd: GR_FLMRD,
    pub gr1_flm1: GR_FLM1,
    pub gr1_flm2: GR_FLM2,
    pub gr1_flm3: GR_FLM3,
    pub gr1_flm5: GR_FLM5,
    pub gr1_flm6: GR_FLM6,
    pub gr1_ab1: GR_AB1,
    pub gr1_ab2: GR_AB2,
    pub gr1_ab3: GR_AB3,
    pub gr1_ab4: GR_AB4,
    pub gr1_ab5: GR_AB5,
    pub gr1_ab6: GR_AB6,
    pub gr1_ab7: GR_AB7,
    pub gr1_ab8: GR_AB8,
    pub gr1_ab9: GR_AB9,
    pub gr1_base: GR_BASE,
    pub gr1_clutint: GR_CLUTINT,
    pub gr1_mon: GR_MON,
    pub gr2_ven: GR_VEN,
    pub gr2_flmrd: GR_FLMRD,
    pub gr2_flm1: GR_FLM1,
    pub gr2_flm2: GR_FLM2,
    pub gr2_flm3: GR_FLM3,
    pub gr2_flm5: GR_FLM5,
    pub gr2_flm6: GR_FLM6,
    pub gr2_ab1: GR_AB1,
    pub gr2_ab2: GR_AB2,
    pub gr2_ab3: GR_AB3,
    pub gr2_ab4: GR_AB4,
    pub gr2_ab5: GR_AB5,
    pub gr2_ab6: GR_AB6,
    pub gr2_ab7: GR_AB7,
    pub gr2_ab8: GR_AB8,
    pub gr2_ab9: GR_AB9,
    pub gr2_base: GR_BASE,
    pub gr2_clutint: GR_CLUTINT,
    pub gr2_mon: GR_MON,
    pub gamg_latch: GAM_LATCH,
    pub gam_sw: GAM_SW,
    pub gamg_lut1: GAM_LUT1,
    pub gamg_lut2: GAM_LUT2,
    pub gamg_lut3: GAM_LUT3,
    pub gamg_lut4: GAM_LUT4,
    pub gamg_lut5: GAM_LUT5,
    pub gamg_lut6: GAM_LUT6,
    pub gamg_lut7: GAM_LUT7,
    pub gamg_lut8: GAM_LUT8,
    pub gamg_area1: GAM_AREA1,
    pub gamg_area2: GAM_AREA2,
    pub gamg_area3: GAM_AREA3,
    pub gamg_area4: GAM_AREA4,
    pub gamg_area5: GAM_AREA5,
    pub gamb_latch: GAM_LATCH,
    pub gamb_lut1: GAM_LUT1,
    pub gamb_lut2: GAM_LUT2,
    pub gamb_lut3: GAM_LUT3,
    pub gamb_lut4: GAM_LUT4,
    pub gamb_lut5: GAM_LUT5,
    pub gamb_lut6: GAM_LUT6,
    pub gamb_lut7: GAM_LUT7,
    pub gamb_lut8: GAM_LUT8,
    pub gamb_area1: GAM_AREA1,
    pub gamb_area2: GAM_AREA2,
    pub gamb_area3: GAM_AREA3,
    pub gamb_area4: GAM_AREA4,
    pub gamb_area5: GAM_AREA5,
    pub gamr_latch: GAM_LATCH,
    pub gamr_lut1: GAM_LUT1,
    pub gamr_lut2: GAM_LUT2,
    pub gamr_lut3: GAM_LUT3,
    pub gamr_lut4: GAM_LUT4,
    pub gamr_lut5: GAM_LUT5,
    pub gamr_lut6: GAM_LUT6,
    pub gamr_lut7: GAM_LUT7,
    pub gamr_lut8: GAM_LUT8,
    pub gamr_area1: GAM_AREA1,
    pub gamr_area2: GAM_AREA2,
    pub gamr_area3: GAM_AREA3,
    pub gamr_area4: GAM_AREA4,
    pub gamr_area5: GAM_AREA5,
    pub out_vlatch: OUT_VLATCH,
    pub out_set: OUT_SET,
    pub out_bright1: OUT_BRIGHT1,
    pub out_bright2: OUT_BRIGHT2,
    pub out_contrast: OUT_CONTRAST,
    pub out_pdtha: OUT_PDTHA,
    pub out_clkphase: OUT_CLKPHASE,
    pub tcon_tim: TCON_TIM,
    pub tcon_stva1: TCON_STV1,
    pub tcon_stva2: TCON_STV2,
    pub tcon_stvb1: TCON_STV1,
    pub tcon_stvb2: TCON_STV2,
    pub tcon_stha1: TCON_STH1,
    pub tcon_stha2: TCON_STH2,
    pub tcon_sthb1: TCON_STH1,
    pub tcon_sthb2: TCON_STH2,
    pub tcon_de: TCON_DE,
    pub syscnt_dtcten: SYSCNT_DTCTEN,
    pub syscnt_inten: SYSCNT_INTEN,
    pub syscnt_stclr: SYSCNT_STCLR,
    pub syscnt_stmon: SYSCNT_STMON,
    pub syscnt_panel_clk: SYSCNT_PANEL_CLK,
    /* private fields */

}
Expand description

Register block

Fields§

§gr1_clut0: [GR1_CLUT0; 256]

0x00..0x400 - Color Palette 0 Plane for Graphics 1 Plane

§gr1_clut1: [GR1_CLUT1; 256]

0x400..0x800 - Color Palette 1 Plane for Graphics 1 Plane

§gr2_clut0: [GR2_CLUT0; 256]

0x800..0xc00 - Color Palette 0 Plane for Graphics 2 Plane

§gr2_clut1: [GR2_CLUT1; 256]

0xc00..0x1000 - Color Palette 1 Plane for Graphics 2 Plane

§bg_en: BG_EN

0x1000 - Background Plane Setting Operation Control Register

§bg_peri: BG_PERI

0x1004 - Background Plane Setting Free-Running Period Register

§bg_sync: BG_SYNC

0x1008 - Background Plane Setting Synchronization Position Register

§bg_vsize: BG_VSIZE

0x100c - Background Plane Setting Full Image Vertical Size Register

§bg_hsize: BG_HSIZE

0x1010 - Background Plane Setting Full Image Horizontal Size Register

§bg_bgc: BG_BGC

0x1014 - Background Plane Setting Background Color Register

§bg_mon: BG_MON

0x1018 - Background Plane Setting Status Monitor Register

§gr1_ven: GR_VEN

0x1100 - Graphics %s Register Update Control Register

§gr1_flmrd: GR_FLMRD

0x1104 - Graphics %s Frame Buffer Read Control Register

§gr1_flm1: GR_FLM1

0x1108 - Graphics %s Frame Buffer Control Register 1

§gr1_flm2: GR_FLM2

0x110c - Graphics %s Frame Buffer Control Register 2

§gr1_flm3: GR_FLM3

0x1110 - Graphics %s Frame Buffer Control Register 3

§gr1_flm5: GR_FLM5

0x1118 - Graphics %s Frame Buffer Control Register 5

§gr1_flm6: GR_FLM6

0x111c - Graphics %s Frame Buffer Control Register 6

§gr1_ab1: GR_AB1

0x1120 - Graphics %s Alpha Blending Control Register 1

§gr1_ab2: GR_AB2

0x1124 - Graphics %s Alpha Blending Control Register 2

§gr1_ab3: GR_AB3

0x1128 - Graphics %s Alpha Blending Control Register 3

§gr1_ab4: GR_AB4

0x112c - Graphics %s Alpha Blending Control Register 4

§gr1_ab5: GR_AB5

0x1130 - Graphics %s Alpha Blending Control Register 5

§gr1_ab6: GR_AB6

0x1134 - Graphics %s Alpha Blending Control Register 6

§gr1_ab7: GR_AB7

0x1138 - Graphics %s Alpha Blending Control Register 7

§gr1_ab8: GR_AB8

0x113c - Graphics %s Alpha Blending Control Register 8

§gr1_ab9: GR_AB9

0x1140 - Graphics %s Alpha Blending Control Register 9

§gr1_base: GR_BASE

0x114c - Graphics %s Background Color Control Register

§gr1_clutint: GR_CLUTINT

0x1150 - Graphics %s CLUT Table Interrupt Control Register

§gr1_mon: GR_MON

0x1154 - Graphics %s Status Monitor Register

§gr2_ven: GR_VEN

0x1200 - Graphics %s Register Update Control Register

§gr2_flmrd: GR_FLMRD

0x1204 - Graphics %s Frame Buffer Read Control Register

§gr2_flm1: GR_FLM1

0x1208 - Graphics %s Frame Buffer Control Register 1

§gr2_flm2: GR_FLM2

0x120c - Graphics %s Frame Buffer Control Register 2

§gr2_flm3: GR_FLM3

0x1210 - Graphics %s Frame Buffer Control Register 3

§gr2_flm5: GR_FLM5

0x1218 - Graphics %s Frame Buffer Control Register 5

§gr2_flm6: GR_FLM6

0x121c - Graphics %s Frame Buffer Control Register 6

§gr2_ab1: GR_AB1

0x1220 - Graphics %s Alpha Blending Control Register 1

§gr2_ab2: GR_AB2

0x1224 - Graphics %s Alpha Blending Control Register 2

§gr2_ab3: GR_AB3

0x1228 - Graphics %s Alpha Blending Control Register 3

§gr2_ab4: GR_AB4

0x122c - Graphics %s Alpha Blending Control Register 4

§gr2_ab5: GR_AB5

0x1230 - Graphics %s Alpha Blending Control Register 5

§gr2_ab6: GR_AB6

0x1234 - Graphics %s Alpha Blending Control Register 6

§gr2_ab7: GR_AB7

0x1238 - Graphics %s Alpha Blending Control Register 7

§gr2_ab8: GR_AB8

0x123c - Graphics %s Alpha Blending Control Register 8

§gr2_ab9: GR_AB9

0x1240 - Graphics %s Alpha Blending Control Register 9

§gr2_base: GR_BASE

0x124c - Graphics %s Background Color Control Register

§gr2_clutint: GR_CLUTINT

0x1250 - Graphics %s CLUT Table Interrupt Control Register

§gr2_mon: GR_MON

0x1254 - Graphics %s Status Monitor Register

§gamg_latch: GAM_LATCH

0x1300 - Gamma %s Register Update Control Register

§gam_sw: GAM_SW

0x1304 - Gamma Correction Block Function Switch Register

§gamg_lut1: GAM_LUT1

0x1308 - Gamma %s Correction Block Table Setting Register 1

§gamg_lut2: GAM_LUT2

0x130c - Gamma %s Correction Block Table Setting Register 2

§gamg_lut3: GAM_LUT3

0x1310 - Gamma %s Correction Block Table Setting Register 3

§gamg_lut4: GAM_LUT4

0x1314 - Gamma %s Correction Block Table Setting Register 4

§gamg_lut5: GAM_LUT5

0x1318 - Gamma %s Correction Block Table Setting Register 5

§gamg_lut6: GAM_LUT6

0x131c - Gamma %s Correction Block Table Setting Register 6

§gamg_lut7: GAM_LUT7

0x1320 - Gamma %s Correction Block Table Setting Register 7

§gamg_lut8: GAM_LUT8

0x1324 - Gamma %s Correction Block Table Setting Register 8

§gamg_area1: GAM_AREA1

0x1328 - Gamma %s Correction Block Area Setting Register 1

§gamg_area2: GAM_AREA2

0x132c - Gamma %s Correction Block Area Setting Register 2

§gamg_area3: GAM_AREA3

0x1330 - Gamma %s Correction Block Area Setting Register 3

§gamg_area4: GAM_AREA4

0x1334 - Gamma %s Correction Block Area Setting Register 4

§gamg_area5: GAM_AREA5

0x1338 - Gamma %s Correction Block Area Setting Register 5

§gamb_latch: GAM_LATCH

0x1340 - Gamma %s Register Update Control Register

§gamb_lut1: GAM_LUT1

0x1348 - Gamma %s Correction Block Table Setting Register 1

§gamb_lut2: GAM_LUT2

0x134c - Gamma %s Correction Block Table Setting Register 2

§gamb_lut3: GAM_LUT3

0x1350 - Gamma %s Correction Block Table Setting Register 3

§gamb_lut4: GAM_LUT4

0x1354 - Gamma %s Correction Block Table Setting Register 4

§gamb_lut5: GAM_LUT5

0x1358 - Gamma %s Correction Block Table Setting Register 5

§gamb_lut6: GAM_LUT6

0x135c - Gamma %s Correction Block Table Setting Register 6

§gamb_lut7: GAM_LUT7

0x1360 - Gamma %s Correction Block Table Setting Register 7

§gamb_lut8: GAM_LUT8

0x1364 - Gamma %s Correction Block Table Setting Register 8

§gamb_area1: GAM_AREA1

0x1368 - Gamma %s Correction Block Area Setting Register 1

§gamb_area2: GAM_AREA2

0x136c - Gamma %s Correction Block Area Setting Register 2

§gamb_area3: GAM_AREA3

0x1370 - Gamma %s Correction Block Area Setting Register 3

§gamb_area4: GAM_AREA4

0x1374 - Gamma %s Correction Block Area Setting Register 4

§gamb_area5: GAM_AREA5

0x1378 - Gamma %s Correction Block Area Setting Register 5

§gamr_latch: GAM_LATCH

0x1380 - Gamma %s Register Update Control Register

§gamr_lut1: GAM_LUT1

0x1388 - Gamma %s Correction Block Table Setting Register 1

§gamr_lut2: GAM_LUT2

0x138c - Gamma %s Correction Block Table Setting Register 2

§gamr_lut3: GAM_LUT3

0x1390 - Gamma %s Correction Block Table Setting Register 3

§gamr_lut4: GAM_LUT4

0x1394 - Gamma %s Correction Block Table Setting Register 4

§gamr_lut5: GAM_LUT5

0x1398 - Gamma %s Correction Block Table Setting Register 5

§gamr_lut6: GAM_LUT6

0x139c - Gamma %s Correction Block Table Setting Register 6

§gamr_lut7: GAM_LUT7

0x13a0 - Gamma %s Correction Block Table Setting Register 7

§gamr_lut8: GAM_LUT8

0x13a4 - Gamma %s Correction Block Table Setting Register 8

§gamr_area1: GAM_AREA1

0x13a8 - Gamma %s Correction Block Area Setting Register 1

§gamr_area2: GAM_AREA2

0x13ac - Gamma %s Correction Block Area Setting Register 2

§gamr_area3: GAM_AREA3

0x13b0 - Gamma %s Correction Block Area Setting Register 3

§gamr_area4: GAM_AREA4

0x13b4 - Gamma %s Correction Block Area Setting Register 4

§gamr_area5: GAM_AREA5

0x13b8 - Gamma %s Correction Block Area Setting Register 5

§out_vlatch: OUT_VLATCH

0x13c0 - Output Control Block Register Update Control Register

§out_set: OUT_SET

0x13c4 - Output Control Block Output Interface Register

§out_bright1: OUT_BRIGHT1

0x13c8 - Output Control Block Brightness Correction Register 1

§out_bright2: OUT_BRIGHT2

0x13cc - Output Control Block Brightness Correction Register 2

§out_contrast: OUT_CONTRAST

0x13d0 - Output Control Block Contrast Correction Register

§out_pdtha: OUT_PDTHA

0x13d4 - Output Control Block Panel Dither Correction Register

§out_clkphase: OUT_CLKPHASE

0x13e4 - Output Control Block Output Phase Control Register

§tcon_tim: TCON_TIM

0x1404 - TCON Reference Timing Setting Register

§tcon_stva1: TCON_STV1

0x1408 - TCON Vertical Timing Setting Register %s1

§tcon_stva2: TCON_STV2

0x140c - TCON Vertical Timing Setting Register %s2

§tcon_stvb1: TCON_STV1

0x1410 - TCON Vertical Timing Setting Register %s1

§tcon_stvb2: TCON_STV2

0x1414 - TCON Vertical Timing Setting Register %s2

§tcon_stha1: TCON_STH1

0x1418 - TCON Horizontal Timing Setting Register STH%s1

§tcon_stha2: TCON_STH2

0x141c - TCON Horizontal Timing Setting Register STH%s2

§tcon_sthb1: TCON_STH1

0x1420 - TCON Horizontal Timing Setting Register STH%s1

§tcon_sthb2: TCON_STH2

0x1424 - TCON Horizontal Timing Setting Register STH%s2

§tcon_de: TCON_DE

0x1428 - TCON Data Enable Polarity Setting Register

§syscnt_dtcten: SYSCNT_DTCTEN

0x1440 - System Control Block State Detection Control Register

§syscnt_inten: SYSCNT_INTEN

0x1444 - System Control Block Interrupt Request Enable Control Register

§syscnt_stclr: SYSCNT_STCLR

0x1448 - System Control Block Status Clear Register

§syscnt_stmon: SYSCNT_STMON

0x144c - System Control Block Status Monitor Register

§syscnt_panel_clk: SYSCNT_PANEL_CLK

0x1450 - System Control Block Version and Panel Clock Control Register

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