Crate ra4e2_pac

Crate ra4e2_pac 

Source
Expand description

Arm Cortex-M33 based Microcontroller RA4E2 group

Re-exports§

pub use self::Interrupt as interrupt;
pub use common::*;

Modules§

adc120
agtw0
bus
cac
cache
canfd_b
cec
common
cpscu
crc
dac12
dbg
dma
dmac0
doc
dtc
eccmb
elc
faci
fcache
flad
gpt16e0
gpt_ops
i3c
icu
interrupt_handlers
iwdt
mstp
pfs
poeg
port0
port1
pscu
rmpu
rtc
sci0
spi0
sram
ssie0
sysc
tsd
tsn
tzf
usbfs
wdt

Structs§

Adc120
Agtw0
Bus
CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
Cac
Cache
CanfdB
Cec
CorePeripherals
Core peripherals
Cpscu
Crc
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
Dac12
Dbg
Dma
Dmac0
Doc
Dtc
Eccmb
Elc
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
Faci
Fcache
Flad
Gpt16E0
GptOps
I3C
ITM
Instrumentation Trace Macrocell
Icu
Iwdt
MPU
Memory Protection Unit
Mstp
NVIC
Nested Vector Interrupt Controller
Peripherals
Required for compatibility with RTIC and other frameworks
Pfs
Poeg
Port0
Port1
Pscu
Rmpu
Rtc
SCB
System Control Block
SYST
SysTick: System Timer
Sci0
Spi0
Sram
Ssie0
Sysc
TPIU
Trace Port Interface Unit
Tsd
Tsn
Tzf
Usbfs
Wdt

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

ADC120
AGTW0
AGTW1
BUS
CAC
CACHE
CANFD_B
CEC
CPSCU
CRC
DAC12
DBG
DMA
DMAC0
DMAC1
DMAC2
DMAC3
DMAC4
DMAC5
DMAC6
DMAC7
DOC
DTC
ECCMB
ELC
FACI
FCACHE
FLAD
GPT16E0
GPT16E1
GPT16E4
GPT16E5
GPT_OPS
I3C
ICU
IWDT
MSTP
NVIC_PRIO_BITS
Number available in the NVIC for configuring priority
PFS
POEG
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT8
PSCU
RMPU
RTC
SCI0
SCI9
SPI0
SPI1
SRAM
SSIE0
SYSC
TSD
TSN
TZF
USBFS
WDT

Attribute Macros§

interrupt