Struct qn908x_rs::usart0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cfg: CFG,
    pub ctl: CTL,
    pub stat: STAT,
    pub intenset: INTENSET,
    pub intenclr: INTENCLR,
    pub brg: BRG,
    pub intstat: INTSTAT,
    pub osr: OSR,
    pub addr: ADDR,
    pub fifocfg: FIFOCFG,
    pub fifostat: FIFOSTAT,
    pub fifotrig: FIFOTRIG,
    pub fifointenset: FIFOINTENSET,
    pub fifointenclr: FIFOINTENCLR,
    pub fifointstat: FIFOINTSTAT,
    pub fifowr: FIFOWR,
    pub fiford: FIFORD,
    pub fifordnopop: FIFORDNOPOP,
    pub id: ID,
    // some fields omitted
}

Register block

Fields

cfg: CFG

0x00 - USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

ctl: CTL

0x04 - USART Control register. USART control settings that are more likely to change during operation.

stat: STAT

0x08 - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.

intenset: INTENSET

0x0c - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

intenclr: INTENCLR

0x10 - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

brg: BRG

0x20 - Baud Rate Generator register. 16-bit integer baud rate divisor value.

intstat: INTSTAT

0x24 - Interrupt status register. Reflects interrupts that are currently enabled.

osr: OSR

0x28 - Oversample selection register for asynchronous communication.

addr: ADDR

0x2c - Address register for automatic address matching.

fifocfg: FIFOCFG

0xe00 - FIFO configuration and enable register.

fifostat: FIFOSTAT

0xe04 - FIFO status register.

fifotrig: FIFOTRIG

0xe08 - FIFO trigger settings for interrupt and DMA request.

fifointenset: FIFOINTENSET

0xe10 - FIFO interrupt enable set (enable) and read register.

fifointenclr: FIFOINTENCLR

0xe14 - FIFO interrupt enable clear (disable) and read register.

fifointstat: FIFOINTSTAT

0xe18 - FIFO interrupt status register.

fifowr: FIFOWR

0xe20 - FIFO write data.

fiford: FIFORD

0xe30 - FIFO read data.

fifordnopop: FIFORDNOPOP

0xe40 - FIFO data read with no FIFO pop.

id: ID

0xffc - USART module Identification. This value appears in the shared Flexcomm peripheral ID register when USART is selected.

Trait Implementations