pub struct MachineForX86Builder<S: State = Empty> { /* private fields */ }Expand description
Use builder syntax to set the inputs and finish with build().
Implementations§
Source§impl<S: State> MachineForX86Builder<S>
impl<S: State> MachineForX86Builder<S>
Sourcepub fn build(self) -> MachineForX86where
S: IsComplete,
pub fn build(self) -> MachineForX86where
S: IsComplete,
Finish building and return the requested object
Sourcepub fn machine_type(
self,
value: MachineX86_64,
) -> MachineForX86Builder<SetMachineType<S>>where
S::MachineType: IsUnset,
pub fn machine_type(
self,
value: MachineX86_64,
) -> MachineForX86Builder<SetMachineType<S>>where
S::MachineType: IsUnset,
Required.
Sourcepub fn accel(self, value: Vec<AccelType>) -> MachineForX86Builder<SetAccel<S>>where
S::Accel: IsUnset,
pub fn accel(self, value: Vec<AccelType>) -> MachineForX86Builder<SetAccel<S>>where
S::Accel: IsUnset,
Sourcepub fn maybe_accel(
self,
value: Option<Vec<AccelType>>,
) -> MachineForX86Builder<SetAccel<S>>where
S::Accel: IsUnset,
pub fn maybe_accel(
self,
value: Option<Vec<AccelType>>,
) -> MachineForX86Builder<SetAccel<S>>where
S::Accel: IsUnset,
Sourcepub fn vmport(self, value: OnOffAuto) -> MachineForX86Builder<SetVmport<S>>where
S::Vmport: IsUnset,
pub fn vmport(self, value: OnOffAuto) -> MachineForX86Builder<SetVmport<S>>where
S::Vmport: IsUnset,
Sourcepub fn maybe_vmport(
self,
value: Option<OnOffAuto>,
) -> MachineForX86Builder<SetVmport<S>>where
S::Vmport: IsUnset,
pub fn maybe_vmport(
self,
value: Option<OnOffAuto>,
) -> MachineForX86Builder<SetVmport<S>>where
S::Vmport: IsUnset,
Sourcepub fn dump_guest_core(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetDumpGuestCore<S>>where
S::DumpGuestCore: IsUnset,
pub fn dump_guest_core(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetDumpGuestCore<S>>where
S::DumpGuestCore: IsUnset,
Sourcepub fn maybe_dump_guest_core(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetDumpGuestCore<S>>where
S::DumpGuestCore: IsUnset,
pub fn maybe_dump_guest_core(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetDumpGuestCore<S>>where
S::DumpGuestCore: IsUnset,
Sourcepub fn mem_merge(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetMemMerge<S>>where
S::MemMerge: IsUnset,
pub fn mem_merge(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetMemMerge<S>>where
S::MemMerge: IsUnset,
Sourcepub fn maybe_mem_merge(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetMemMerge<S>>where
S::MemMerge: IsUnset,
pub fn maybe_mem_merge(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetMemMerge<S>>where
S::MemMerge: IsUnset,
Sourcepub fn aes_key_wrap(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetAesKeyWrap<S>>where
S::AesKeyWrap: IsUnset,
pub fn aes_key_wrap(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetAesKeyWrap<S>>where
S::AesKeyWrap: IsUnset,
Sourcepub fn maybe_aes_key_wrap(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetAesKeyWrap<S>>where
S::AesKeyWrap: IsUnset,
pub fn maybe_aes_key_wrap(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetAesKeyWrap<S>>where
S::AesKeyWrap: IsUnset,
Sourcepub fn dea_key_wrap(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetDeaKeyWrap<S>>where
S::DeaKeyWrap: IsUnset,
pub fn dea_key_wrap(
self,
value: OnOffDefaultOn,
) -> MachineForX86Builder<SetDeaKeyWrap<S>>where
S::DeaKeyWrap: IsUnset,
Sourcepub fn maybe_dea_key_wrap(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetDeaKeyWrap<S>>where
S::DeaKeyWrap: IsUnset,
pub fn maybe_dea_key_wrap(
self,
value: Option<OnOffDefaultOn>,
) -> MachineForX86Builder<SetDeaKeyWrap<S>>where
S::DeaKeyWrap: IsUnset,
Sourcepub fn nvdimm(
self,
value: OnOffDefaultOff,
) -> MachineForX86Builder<SetNvdimm<S>>where
S::Nvdimm: IsUnset,
pub fn nvdimm(
self,
value: OnOffDefaultOff,
) -> MachineForX86Builder<SetNvdimm<S>>where
S::Nvdimm: IsUnset,
Sourcepub fn maybe_nvdimm(
self,
value: Option<OnOffDefaultOff>,
) -> MachineForX86Builder<SetNvdimm<S>>where
S::Nvdimm: IsUnset,
pub fn maybe_nvdimm(
self,
value: Option<OnOffDefaultOff>,
) -> MachineForX86Builder<SetNvdimm<S>>where
S::Nvdimm: IsUnset,
Sourcepub fn memory_encryption(
self,
value: String,
) -> MachineForX86Builder<SetMemoryEncryption<S>>where
S::MemoryEncryption: IsUnset,
pub fn memory_encryption(
self,
value: String,
) -> MachineForX86Builder<SetMemoryEncryption<S>>where
S::MemoryEncryption: IsUnset,
Sourcepub fn maybe_memory_encryption(
self,
value: Option<String>,
) -> MachineForX86Builder<SetMemoryEncryption<S>>where
S::MemoryEncryption: IsUnset,
pub fn maybe_memory_encryption(
self,
value: Option<String>,
) -> MachineForX86Builder<SetMemoryEncryption<S>>where
S::MemoryEncryption: IsUnset,
Sourcepub fn hmat(self, value: OnOffDefaultOff) -> MachineForX86Builder<SetHmat<S>>where
S::Hmat: IsUnset,
pub fn hmat(self, value: OnOffDefaultOff) -> MachineForX86Builder<SetHmat<S>>where
S::Hmat: IsUnset,
Sourcepub fn maybe_hmat(
self,
value: Option<OnOffDefaultOff>,
) -> MachineForX86Builder<SetHmat<S>>where
S::Hmat: IsUnset,
pub fn maybe_hmat(
self,
value: Option<OnOffDefaultOff>,
) -> MachineForX86Builder<SetHmat<S>>where
S::Hmat: IsUnset,
Optional (Some / Option setters).
Allocate auxiliary guest RAM as an anonymous file that is shareable with an external process. This option applies to memory allocated as a side effect of creating various devices. It does not apply to memory-backend-objects, whether explicitly specified on the command line, or implicitly created by the -m command line option. The default is off.
Optional (Some / Option setters).
Allocate auxiliary guest RAM as an anonymous file that is shareable with an external process. This option applies to memory allocated as a side effect of creating various devices. It does not apply to memory-backend-objects, whether explicitly specified on the command line, or implicitly created by the -m command line option. The default is off.
Sourcepub fn memory_backend(
self,
value: String,
) -> MachineForX86Builder<SetMemoryBackend<S>>where
S::MemoryBackend: IsUnset,
pub fn memory_backend(
self,
value: String,
) -> MachineForX86Builder<SetMemoryBackend<S>>where
S::MemoryBackend: IsUnset,
Sourcepub fn maybe_memory_backend(
self,
value: Option<String>,
) -> MachineForX86Builder<SetMemoryBackend<S>>where
S::MemoryBackend: IsUnset,
pub fn maybe_memory_backend(
self,
value: Option<String>,
) -> MachineForX86Builder<SetMemoryBackend<S>>where
S::MemoryBackend: IsUnset,
Sourcepub fn cxl_fmw(self, value: CxlFmw) -> MachineForX86Builder<SetCxlFmw<S>>where
S::CxlFmw: IsUnset,
pub fn cxl_fmw(self, value: CxlFmw) -> MachineForX86Builder<SetCxlFmw<S>>where
S::CxlFmw: IsUnset,
Optional (Some / Option setters).
Define a CXL Fixed Memory Window (CFMW).
Described in the CXL 2.0 ECN: CEDT CFMWS & QTG _DSM.
They are regions of Host Physical Addresses (HPA) on a system which may be interleaved across one or more CXL host bridges. The system software will assign particular devices into these windows and configure the downstream Host-managed Device Memory (HDM) decoders in root ports, switch ports and devices appropriately to meet the interleave requirements before enabling the memory devices.
targets.X=target provides the mapping to CXL host bridges
which may be identified by the id provided in the -device entry.
Multiple entries are needed to specify all the targets when
the fixed memory window represents interleaved memory. X is the
target index from 0.
size=size sets the size of the CFMW. This must be a multiple of
256MiB. The region will be aligned to 256MiB but the location is
platform and configuration dependent.
interleave-granularity=granularity sets the granularity of
interleave. Default 256 (bytes). Only 256, 512, 1k, 2k,
4k, 8k and 16k granularities supported.
Sourcepub fn maybe_cxl_fmw(
self,
value: Option<CxlFmw>,
) -> MachineForX86Builder<SetCxlFmw<S>>where
S::CxlFmw: IsUnset,
pub fn maybe_cxl_fmw(
self,
value: Option<CxlFmw>,
) -> MachineForX86Builder<SetCxlFmw<S>>where
S::CxlFmw: IsUnset,
Optional (Some / Option setters).
Define a CXL Fixed Memory Window (CFMW).
Described in the CXL 2.0 ECN: CEDT CFMWS & QTG _DSM.
They are regions of Host Physical Addresses (HPA) on a system which may be interleaved across one or more CXL host bridges. The system software will assign particular devices into these windows and configure the downstream Host-managed Device Memory (HDM) decoders in root ports, switch ports and devices appropriately to meet the interleave requirements before enabling the memory devices.
targets.X=target provides the mapping to CXL host bridges
which may be identified by the id provided in the -device entry.
Multiple entries are needed to specify all the targets when
the fixed memory window represents interleaved memory. X is the
target index from 0.
size=size sets the size of the CFMW. This must be a multiple of
256MiB. The region will be aligned to 256MiB but the location is
platform and configuration dependent.
interleave-granularity=granularity sets the granularity of
interleave. Default 256 (bytes). Only 256, 512, 1k, 2k,
4k, 8k and 16k granularities supported.
Sourcepub fn smp_cache(
self,
value: Vec<SmpCache>,
) -> MachineForX86Builder<SetSmpCache<S>>where
S::SmpCache: IsUnset,
pub fn smp_cache(
self,
value: Vec<SmpCache>,
) -> MachineForX86Builder<SetSmpCache<S>>where
S::SmpCache: IsUnset,
Optional (Some / Option setters).
Define cache properties for SMP system.
cache=cachename specifies the cache that the properties will be
applied on. This field is the combination of cache level and cache
type. It supports l1d (L1 data cache), l1i (L1 instruction
cache), l2 (L2 unified cache) and l3 (L3 unified cache).
topology=topologylevel sets the cache topology level. It accepts
CPU topology levels including core, module, cluster, die,
socket, book, drawer and a special value default. If
default is set, then the cache topology will follow the architecture’s
default cache topology model. If another topology level is set, the cache
will be shared at corresponding CPU topology level. For example,
topology=core makes the cache shared by all threads within a core.
The omitting cache will default to using the default level.
The default cache topology model for an i386 PC machine is as follows:
l1d, l1i, and l2 caches are per core, while the l3
cache is per die.
Sourcepub fn maybe_smp_cache(
self,
value: Option<Vec<SmpCache>>,
) -> MachineForX86Builder<SetSmpCache<S>>where
S::SmpCache: IsUnset,
pub fn maybe_smp_cache(
self,
value: Option<Vec<SmpCache>>,
) -> MachineForX86Builder<SetSmpCache<S>>where
S::SmpCache: IsUnset,
Optional (Some / Option setters).
Define cache properties for SMP system.
cache=cachename specifies the cache that the properties will be
applied on. This field is the combination of cache level and cache
type. It supports l1d (L1 data cache), l1i (L1 instruction
cache), l2 (L2 unified cache) and l3 (L3 unified cache).
topology=topologylevel sets the cache topology level. It accepts
CPU topology levels including core, module, cluster, die,
socket, book, drawer and a special value default. If
default is set, then the cache topology will follow the architecture’s
default cache topology model. If another topology level is set, the cache
will be shared at corresponding CPU topology level. For example,
topology=core makes the cache shared by all threads within a core.
The omitting cache will default to using the default level.
The default cache topology model for an i386 PC machine is as follows:
l1d, l1i, and l2 caches are per core, while the l3
cache is per die.