Struct qcs_api::models::architecture::Architecture

pub struct Architecture {
    pub edges: Vec<Edge>,
    pub family: Option<Box<Family>>,
    pub nodes: Vec<Node>,
}

Architecture : Represents the logical underlying architecture of a quantum processor. The architecture is defined in detail by the nodes and edges that constitute the quantum processor. This defines the set of all nodes that could be operated upon, and indicates to some approximation their physical layout. The main purpose of this is to support geometry calculations that are independent of the available operations, and rendering ISA-based information. Architecture layouts are defined by the family, as follows. The "Aspen" family of quantum processor indicates a 2D planar grid layout of octagon unit cells. The node_id in this architecture is computed as :math:100 p_y + 10 p_x + p_u where :math:p_y is the zero-based Y position in the unit cell grid, :math:p_x is the zero-based X position in the unit cell grid, and :math:p_u is the zero-based position in the octagon unit cell and always ranges from 0 to 7. This scheme has a natural size limit of a 10x10 unit cell grid, which permits the architecture to scale up to 800 nodes. Note that the operations that are actually available are defined entirely by Operation instances. The presence of a node or edge in the Architecture model provides no guarantee that any 1Q or 2Q operation will be available to users writing QUIL programs.

Fields

edges: Vec<Edge>

A list of all computational edges in the instruction set architecture.

family: Option<Box<Family>>

The architecture family. The nodes and edges conform to this family.

nodes: Vec<Node>

A list of all computational nodes in the instruction set architecture.

Implementations

impl Architecture

pub fn new(
    edges: Vec<Edge>,
    family: Option<Family>,
    nodes: Vec<Node>
) -> Architecture

Represents the logical underlying architecture of a quantum processor. The architecture is defined in detail by the nodes and edges that constitute the quantum processor. This defines the set of all nodes that could be operated upon, and indicates to some approximation their physical layout. The main purpose of this is to support geometry calculations that are independent of the available operations, and rendering ISA-based information. Architecture layouts are defined by the family, as follows. The "Aspen" family of quantum processor indicates a 2D planar grid layout of octagon unit cells. The node_id in this architecture is computed as :math:100 p_y + 10 p_x + p_u where :math:p_y is the zero-based Y position in the unit cell grid, :math:p_x is the zero-based X position in the unit cell grid, and :math:p_u is the zero-based position in the octagon unit cell and always ranges from 0 to 7. This scheme has a natural size limit of a 10x10 unit cell grid, which permits the architecture to scale up to 800 nodes. Note that the operations that are actually available are defined entirely by Operation instances. The presence of a node or edge in the Architecture model provides no guarantee that any 1Q or 2Q operation will be available to users writing QUIL programs.

Trait Implementations

impl Clone for Architecture

fn clone(&self) -> Architecture

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Architecture

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Architecture

fn default() -> Architecture

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for Architecture

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error> where
    __D: Deserializer<'de>, 

Deserialize this value from the given Serde deserializer.

impl PartialEq<Architecture> for Architecture

fn eq(&self, other: &Architecture) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Architecture) -> bool

This method tests for !=.

impl Serialize for Architecture

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error> where
    __S: Serializer, 

Serialize this value into the given Serde serializer.

impl StructuralPartialEq for Architecture