Struct ADC_InitTypeDef 

#[repr(C)]
pub struct ADC_InitTypeDef {

    pub ClockPrescaler: u32,
    pub Resolution: u32,
    pub DataAlign: u32,
    pub ScanConvMode: u32,
    pub EOCSelection: u32,
    pub LowPowerAutoWait: FunctionalState,
    pub ContinuousConvMode: FunctionalState,
    pub DiscontinuousConvMode: FunctionalState,
    pub ExternalTrigConv: u32,
    pub ExternalTrigConvEdge: u32,
    pub DMAContinuousRequests: FunctionalState,
    pub Overrun: u32,
    pub SamplingTimeCommon: u32,
}

@brief Structure definition of ADC initialization and regular group @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either: - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter ‘ClockPrescaler’) - For all parameters except ‘ClockPrescaler’ and ‘resolution’: ADC enabled without conversion on going on regular group. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Fields

ClockPrescaler: u32

< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. This parameter can be a value of @ref ADC_ClockPrescaler Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if the ADC is disabled

Resolution: u32

< Configures the ADC resolution. This parameter can be a value of @ref ADC_Resolution

DataAlign: u32

< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_Data_align

ScanConvMode: u32

< Configures the sequencer of regular group. This parameter can be associated to parameter ‘DiscontinuousConvMode’ to have main sequence subdivided in successive parts. Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other PY32 devices): If only 1 channel is set: Conversion is performed in single mode. If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, …). Scan direction can be set to forward (from channel 0 to channel 12) or backward (from channel 18 to channel 0). This parameter can be a value of @ref ADC_Scan_mode

EOCSelection: u32

< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of @ref ADC_EOCSelection.

LowPowerAutoWait: FunctionalState

< Selects the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion.

ContinuousConvMode: FunctionalState

< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

DiscontinuousConvMode: FunctionalState

< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter ‘ScanConvMode’). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE Note: Number of discontinuous ranks increment is fixed to one-by-one.

ExternalTrigConv: u32

< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. This parameter can be a value of @ref ADC_External_trigger_source_Regular

ExternalTrigConvEdge: u32

< Selects the external trigger edge of regular group. If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_External_trigger_edge_Regular

DMAContinuousRequests: FunctionalState

< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) or in Continuous mode (DMA transfer unlimited, whatever number of conversions). Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be set to ENABLE or DISABLE.

Overrun: u32

< Select the behaviour in case of overrun: data preserved or overwritten This parameter has an effect on regular group only, including in DMA mode. This parameter can be a value of @ref ADC_Overrun

SamplingTimeCommon: u32

< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). Note: On PY32F0 devices, the sampling time setting is common to all channels. On some other PY32 devices, this parameter in channel wise and is located into ADC channel initialization structure. This parameter can be a value of @ref ADC_sampling_times Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17us).

Trait Implementations

impl Clone for ADC_InitTypeDef

fn clone(&self) -> ADC_InitTypeDef

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ADC_InitTypeDef

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for ADC_InitTypeDef