Struct ps2::Controller [−][src]
pub struct Controller { /* fields omitted */ }
Expand description
The PS/2 controller.
Provides the functionality of an Intel 8042 chip. Many computers nowadays don’t have PS/2 connectors, but emulate the mouse and keyboard as PS/2 devices through USB. The implementation of this emulation is usually different from manufacturer to manufacturer and cannot always be relied upon to perform correctly. Therefore, if you’re writing an operating system, you should disable this legacy support once the USB controller has been initialized.
Implementations
Create a handle to the PS/2 controller. Uses a default IO timeout of 10,000 tries.
Safety
Ensure that IO ports 0x60
and 0x64
are not accessed by any other code, and that only
one Controller
accesses those ports at any point in time.
Like new
, but allows specifying an IO timeout, which is the number of times an IO
operation will be attempted before returning ControllerError::Timeout
.
Read the status register of the controller.
Read a byte from the data buffer once it is full.
If there is no data available to read within the configured timeout, this will return
ControllerError::Timeout
.
Write a byte to the data buffer once it is empty.
If a write cannot be performed within the configured timeout, this will return
ControllerError::Timeout
.
Read a byte from the controller’s internal RAM.
The desired byte index must be between 0 and 31. Byte 0 is also known as the configuration byte or command byte.
pub fn write_internal_ram(
&mut self,
byte_number: u8,
data: u8
) -> Result<(), ControllerError>
pub fn write_internal_ram(
&mut self,
byte_number: u8,
data: u8
) -> Result<(), ControllerError>
Write a byte to the controller’s internal RAM.
The desired byte index must be between 0 and 31. Byte 0 is also known as the configuration byte or command byte.
Read the configuration byte (or command byte) of the controller. This is the same as reading byte 0 of the internal RAM.
Write the configuration byte (or command byte) of the controller. This is the same as writing to byte 0 of the internal RAM.
Disable the mouse. Sets the ControllerConfigFlags::DISABLE_MOUSE
flag.
Enable the mouse. Clears the ControllerConfigFlags::DISABLE_MOUSE
flag.
Perform a self-test on the mouse.
Returns ControllerError::TestFailed
if the test fails.
Perform a self-test on the controller.
Returns ControllerError::TestFailed
if the test fails.
Perform a self-test on the keyboard.
Returns ControllerError::TestFailed
if the test fails.
Dump all bytes of the controller’s internal RAM.
Disable the keyboard.
Sets the ControllerConfigFlags::DISABLE_KEYBOARD
flag.
Enable the keyboard.
Clears the ControllerConfigFlags::DISABLE_KEYBOARD
flag.
Read the state of the controller’s input port.
Write the low nibble of the controller’s input port to the low nibble of the controller status register.
Write the high nibble of the controller’s input port to the high nibble of the controller status register.
Read the state of the controller’s output port.
Write the state of the controller’s output port.
Write a byte to the data buffer as if it were received from the keyboard.
This will trigger an interrupt if interrupts are enabled.
Write a byte to the data buffer as if it were received from the mouse.
This will trigger an interrupt if interrupts are enabled.
Write a byte to the mouse’s data buffer.
Read the state of the controller’s test port.
Pulse the low nibble of the given byte onto the lower nibble of the controller output port.