Struct probe_rs::probe::espusbjtag::EspUsbJtag

pub struct EspUsbJtag { /* private fields */ }

A USB JTAG interface built into certain ESP32 chips.

Trait Implementations

impl Debug for EspUsbJtag

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl DebugProbe for EspUsbJtag

fn select_protocol( &mut self, protocol: WireProtocol ) -> Result<(), DebugProbeError>

Selects the transport protocol to be used by the debug probe.

fn active_protocol(&self) -> Option<WireProtocol>

Get the transport protocol currently in active use by the debug probe.

fn get_name(&self) -> &'static str

Get human readable name for the probe.

fn speed_khz(&self) -> u32

Get the currently used maximum speed for the debug protocol in kHz.

fn set_speed(&mut self, speed_khz: u32) -> Result<u32, DebugProbeError>

Set the speed in kHz used for communication with the target device.

fn set_scan_chain( &mut self, scan_chain: Vec<ScanChainElement> ) -> Result<(), DebugProbeError>

Set the JTAG scan chain information for the target under debug.

fn scan_chain(&self) -> Result<&[ScanChainElement], DebugProbeError>

Returns the JTAG scan chain

fn select_jtag_tap(&mut self, index: usize) -> Result<(), DebugProbeError>

Selects the JTAG TAP to be used for communication.

fn attach(&mut self) -> Result<(), DebugProbeError>

Attach to the chip.

fn detach(&mut self) -> Result<(), Error>

Detach from the chip.

fn target_reset(&mut self) -> Result<(), DebugProbeError>

This should hard reset the target device.

fn target_reset_assert(&mut self) -> Result<(), DebugProbeError>

This should assert the reset pin of the target via debug probe.

fn target_reset_deassert(&mut self) -> Result<(), DebugProbeError>

This should deassert the reset pin of the target via debug probe.

fn try_get_riscv_interface_builder<'probe>( &'probe mut self ) -> Result<Box<dyn RiscvInterfaceBuilder<'probe> + 'probe>, DebugProbeError>

Try to get a RiscvInterfaceBuilder object, which can be used to set up a communication interface with chips using the RISC-V architecture.

fn get_swo_interface(&self) -> Option<&dyn SwoAccess>

Get a SWO interface from the debug probe.

fn get_swo_interface_mut(&mut self) -> Option<&mut dyn SwoAccess>

Get a mutable SWO interface from the debug probe.

fn has_arm_interface(&self) -> bool

Check if the probe offers an interface to debug ARM chips.

fn has_riscv_interface(&self) -> bool

Check if the probe offers an interface to debug RISC-V chips.

fn into_probe(self: Box<Self>) -> Box<dyn DebugProbe>

Boxes itself.

fn try_as_dap_probe(&mut self) -> Option<&mut dyn DapProbe>

Try creating a DAP interface for the given probe.

fn try_get_arm_interface<'probe>( self: Box<Self> ) -> Result<Box<dyn UninitializedArmProbe + 'probe>, (Box<dyn DebugProbe>, DebugProbeError)>

Get the dedicated interface to debug ARM chips. To check that the probe actually supports this, call DebugProbe::has_arm_interface first.

fn get_target_voltage(&mut self) -> Result<Option<f32>, DebugProbeError>

Reads the target voltage in Volts, if possible. Returns Ok(None) if the probe doesn’t support reading the target voltage.

fn try_get_xtensa_interface<'probe>( &'probe mut self, state: &'probe mut XtensaDebugInterfaceState ) -> Result<XtensaCommunicationInterface<'probe>, DebugProbeError>

Get the dedicated interface to debug Xtensa chips. Ensure that the probe actually supports this by calling DebugProbe::has_xtensa_interface first.

fn has_xtensa_interface(&self) -> bool

Check if the probe offers an interface to debug Xtensa chips.

fn try_into_jlink(&mut self) -> Result<&mut JLink, DebugProbeError>

Try to get a J-Link interface from the debug probe.