Struct probe_rs::architecture::arm::armv8m::Dhcsr

impl Dhcsr

pub fn s_restart_st(&self) -> bool

Restart sticky status. Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request.

The possible values of this bit are:

0: PE has not left Debug state since the last read of DHCSR.
1: PE has left Debug state since the last read of DHCSR.

If the PE is not halted when C_HALT is cleared to zero, it is UNPREDICTABLE whether this bit is set to 1. If DHCSR.C_DEBUGEN == 0 this bit reads as an UNKNOWN value.

This bit clears to zero when read.

Note

If the request to clear C_HALT is made simultaneously with a request to set C_HALT, for example a restart request and external debug request occur together, then the

pub fn s_reset_st(&self) -> bool

Indicates whether the processor has been reset since the last read of DHCSR:

0: No reset since last DHCSR read.
1: At least one reset since last DHCSR read.

This is a sticky bit, that clears to 0 on a read of DHCSR.

pub fn s_retire_st(&self) -> bool

When not in Debug state, indicates whether the processor has completed the execution of an instruction since the last read of DHCSR:

0: No instruction has completed since last DHCSR read.
1: At least one instructions has completed since last DHCSR read.

This is a sticky bit, that clears to 0 on a read of DHCSR.

This bit is UNKNOWN:

after a Local reset, but is set to 1 as soon as the processor completes execution of an instruction.
when S_LOCKUP is set to 1.
when S_HALT is set to 1.

When the processor is not in Debug state, a debugger can check this bit to determine if the processor is stalled on a load, store or fetch access.

pub fn s_fpd(&self) -> bool

Floating-point registers Debuggable. Indicates that FPSCR, VPR, and the Floating-point registers are RAZ/WI in the current PE state when accessed via DCRSR. This reflects !CanDebugAccessFP(). The possible values of this bit are:

0: Floating-point registers accessible.
1: Floating-point registers are RAZ/WI.

If version Armv8.1-M of the architecture is not implemented, this bit is RES0

pub fn s_suide(&self) -> bool

Secure unprivileged halting debug enabled. Indicates whether Secure unprivileged-only halting debug is allowed or active. The possible values of this bit are:

0: Secure invasive halting debug prohibited or not restricted to an unprivileged mode.
1: Unprivileged Secure invasive halting debug enabled.

If the PE is in Non-debug state, this bit reflects the value of UnprivHaltingDebugAllowed(TRUE) && !SecureHaltingDebugAllowed().

The value of this bit does not change whilst the PE remains in Debug state.

If the Security Extension is not implemented, this bit is RES0. If version Armv8.1 of the architecture and UDE are not implemented, this bit is RES0.

pub fn s_nsuide(&self) -> bool

Non-secure unprivileged halting debug enabled. Indicates whether Non-secure unprivileged-only halting debug is allowed or active.

The possible values of this bit are:

0: Non-secure invasive halting debug prohibited or not restricted to an unprivileged mode.
1: Unprivileged Non-secure invasive halting debug enabled.

If the PE is in Non-debug state, this bit reflects the value of UnprivHaltingDebugAllowed(FALSE) && !HaltingDebugAllowed().

The value of this bit does not change whilst the PE remains in Debug state. If version Armv8.1 of the architecture and UDE are not implemented, this bit is RES0

pub fn s_sde(&self) -> bool

Secure debug enabled. Indicates whether Secure invasive debug is allowed. The possible values of this bit are:

0: Secure invasive debug prohibited.
1: Secure invasive debug allowed.

If the PE is in Non-debug state, this bit reflects the value of SecureHaltingDebugAllowed() or UnprivHaltingDebugAllowed(TRUE).

The value of this bit does not change while the PE remains in Debug state.

If the Security Extension is not implemented, this bit is RES0.

pub fn s_lockup(&self) -> bool

Indicates whether the processor is locked up because of an unrecoverable exception:

0 Not locked up.
1 Locked up. See Unrecoverable exception cases on page B1-206 for more information.

This bit can only read as 1 when accessed by a remote debugger using the DAP. The value of 1 indicates that the processor is running but locked up. The bit clears to 0 when the processor enters Debug state.

pub fn s_sleep(&self) -> bool

Indicates whether the processor is sleeping:

0 Not sleeping. 1 Sleeping.

The debugger must set the DHCSR.C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system

pub fn s_halt(&self) -> bool

Indicates whether the processor is in Debug state:

0: Not in Debug state.
1: In Debug state.

pub fn s_regrdy(&self) -> bool

A handshake flag for transfers through the DCRDR:

Writing to DCRSR clears the bit to 0.
Completion of the DCRDR transfer then sets the bit to 1.

For more information about DCRDR transfers see Debug Core Register Data Register, DCRDR on page C1-292.

0: There has been a write to the DCRDR, but the transfer is not complete.
1 The transfer to or from the DCRDR is complete.

This bit is only valid when the processor is in Debug state, otherwise the bit is UNKNOWN.

pub fn c_pmov(&self) -> bool

Halt on PMU overflow control. Request entry to Debug state when a PMU counter overflows.

The possible values of this bit are:

0: No action.
1: If C_DEBUGEN is set to 1, then when a PMU counter is configured to generate an interrupt overflows, the PE sets DHCSR.C_HALT to 1 and DFSR.PMU to 1.

PMU_OVSSET and PMU_OVSCLR indicate which counter or counters triggered the halt.

If the Main Extension is not implemented, this bit is RES0.

If version Armv8.1 of the architecture and PMU are not implemented, this bit is RES0.

This bit resets to zero on a Cold reset.

pub fn c_snapstall(&self) -> bool

Allow imprecise entry to Debug state. The actions on writing to this bit are:

0: No action.
1: Allow imprecise entry to Debug state, for example by forcing any stalled load or store instruction to complete.

Setting this bit to 1 allows a debugger to request imprecise entry to Debug state.

The effect of setting this bit to 1 is UNPREDICTABLE unless the DHCSR write also sets C_DEBUGEN and C_HALT to 1. This means that if the processor is not already in Debug state it enters Debug state when the stalled instruction completes.

Writing 1 to this bit makes the state of the memory system UNPREDICTABLE. Therefore, if a debugger writes 1 to this bit it must reset the processor before leaving Debug state.

Note

A debugger can write to the DHCSR to clear this bit to 0. However, this does not remove the UNPREDICTABLE state of the memory system caused by setting C_SNAPSTALL to 1.
The architecture does not guarantee that setting this bit to 1 will force entry to Debug state.
Arm strongly recommends that a value of 1 is never written to C_SNAPSTALL when the processor is in Debug state.

A power-on reset sets this bit to 0.

pub fn c_maskints(&self) -> bool

When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:

0: Do not mask.
1 Mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:

before the write to DHCSR, the value of the C_HALT bit is 1.
the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.

This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.

The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn c_step(&self) -> bool

Processor step bit. The effects of writes to this bit are:

0: Single-stepping disabled.
1: Single-stepping enabled.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn c_halt(&self) -> bool

Processor halt bit. The effects of writes to this bit are:

0: Request a halted processor to run.
1: Request a running processor to halt.

Table C1-9 on page C1-282 shows the effect of writes to this bit when the processor is in Debug state.

This bit is 0 after a System reset

pub fn c_debugen(&self) -> bool

Halting debug enable bit: 0: Halting debug disabled.
1: Halting debug enabled.

If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.

This bit can only be written from the DAP. Access to the DHCSR from software running on the processor is IMPLEMENTATION DEFINED.

However, writes to this bit from software running on the processor are ignored.

This bit is 0 after a power-on reset.

pub fn set_c_pmov(&mut self, value: bool)

Halt on PMU overflow control. Request entry to Debug state when a PMU counter overflows.

The possible values of this bit are:

0: No action.
1: If C_DEBUGEN is set to 1, then when a PMU counter is configured to generate an interrupt overflows, the PE sets DHCSR.C_HALT to 1 and DFSR.PMU to 1.

PMU_OVSSET and PMU_OVSCLR indicate which counter or counters triggered the halt.

If the Main Extension is not implemented, this bit is RES0.

If version Armv8.1 of the architecture and PMU are not implemented, this bit is RES0.

This bit resets to zero on a Cold reset.

pub fn set_c_snapstall(&mut self, value: bool)

Allow imprecise entry to Debug state. The actions on writing to this bit are:

0: No action.
1: Allow imprecise entry to Debug state, for example by forcing any stalled load or store instruction to complete.

Setting this bit to 1 allows a debugger to request imprecise entry to Debug state.

The effect of setting this bit to 1 is UNPREDICTABLE unless the DHCSR write also sets C_DEBUGEN and C_HALT to 1. This means that if the processor is not already in Debug state it enters Debug state when the stalled instruction completes.

Writing 1 to this bit makes the state of the memory system UNPREDICTABLE. Therefore, if a debugger writes 1 to this bit it must reset the processor before leaving Debug state.

Note

A debugger can write to the DHCSR to clear this bit to 0. However, this does not remove the UNPREDICTABLE state of the memory system caused by setting C_SNAPSTALL to 1.
The architecture does not guarantee that setting this bit to 1 will force entry to Debug state.
Arm strongly recommends that a value of 1 is never written to C_SNAPSTALL when the processor is in Debug state.

A power-on reset sets this bit to 0.

pub fn set_c_maskints(&mut self, value: bool)

When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:

0: Do not mask.
1 Mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:

before the write to DHCSR, the value of the C_HALT bit is 1.
the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.

This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.

The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn set_c_step(&mut self, value: bool)

Processor step bit. The effects of writes to this bit are:

0: Single-stepping disabled.
1: Single-stepping enabled.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn set_c_halt(&mut self, value: bool)

Processor halt bit. The effects of writes to this bit are:

0: Request a halted processor to run.
1: Request a running processor to halt.

Table C1-9 on page C1-282 shows the effect of writes to this bit when the processor is in Debug state.

This bit is 0 after a System reset

pub fn set_c_debugen(&mut self, value: bool)

Halting debug enable bit: 0: Halting debug disabled.
1: Halting debug enabled.

If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.

This bit can only be written from the DAP. Access to the DHCSR from software running on the processor is IMPLEMENTATION DEFINED.

However, writes to this bit from software running on the processor are ignored.

This bit is 0 after a power-on reset.

Trait Implementations§

impl<T> BitRange<T> for Dhcsrwhere
u32: BitRange<T>,

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

impl<T> BitRangeMut<T> for Dhcsrwhere
u32: BitRangeMut<T>,

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Clone for Dhcsr

fn clone(&self) -> Dhcsr

Returns a copy of the value. Read more

1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl Debug for Dhcsr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl From<Dhcsr> for u32

fn from(value: Dhcsr) -> Self

Converts to this type from the input type.

impl From<u32> for Dhcsr

fn from(value: u32) -> Self

Converts to this type from the input type.

impl MemoryMappedRegister for Dhcsr

const ADDRESS: u64 = 3_758_157_296u64

The register’s address in the target memory.

const NAME: &'static str = "DHCSR"

The register’s name.

impl Copy for Dhcsr

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impl UnwindSafe for Dhcsr

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fn bit(&self, bit: usize) -> bool

Get a single bit.

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fn set_bit(&mut self, bit: usize, value: bool)

Set a single bit.

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