Struct probe_rs::architecture::arm::armv8m::Aircr

pub struct Aircr(pub u32);

Application Interrupt and Reset Control Register, AIRCR (see armv8-M Architecture Reference Manual D1.2.3)

Aircr::vectkey must be called before this register can effectively be written!

Tuple Fields

0: u32

Implementations

impl Aircr

pub fn endianness(&self) -> bool

Indicates the memory system data endianness:

0: little endian.
1 big endian.

See Endian support on page A3-44 for more information.

pub fn prigroup(&self) -> u32

Priority grouping, indicates the binary point position. For information about the use of this field see Priority grouping on page B1-527.

This field resets to 0b000.

pub fn sysresetreqs(&self) -> bool

System reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. The possible values of this bit are:

0: SYSRESETREQ functionality is available to both Security states.
1: SYSRESETREQ functionality is only available to Secure state.

This bit is RAZ/WI from Non-secure state. This bit resets to zero on a Warm reset

pub fn sysresetreq(&self) -> bool

System Reset Request:

0 do not request a reset.
1 request reset.

Writing 1 to this bit asserts a signal to request a reset by the external system. The system components that are reset by this request are IMPLEMENTATION DEFINED. A Local reset is required as part of a system reset request.

A Local reset clears this bit to 0.

See Reset management on page B1-208 for more information

pub fn vectclractive(&self) -> bool

Clears all active state information for fixed and configurable exceptions:

0: do not clear state information.
1: clear state information.

The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.

pub fn vectreset(&self) -> bool

Writing 1 to this bit causes a local system reset, see Reset management on page B1-559 for more information. This bit self-clears.

The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.

When the processor is halted in Debug state, if a write to the register writes a 1 to both VECTRESET and SYSRESETREQ, the behavior is UNPREDICTABLE.

This bit is write only.

pub fn set_endianness(&mut self, value: bool)

Indicates the memory system data endianness:

0: little endian.
1 big endian.

See Endian support on page A3-44 for more information.

pub fn set_prigroup(&mut self, value: u32)

Priority grouping, indicates the binary point position. For information about the use of this field see Priority grouping on page B1-527.

This field resets to 0b000.

pub fn set_sysresetreqs(&mut self, value: bool)

System reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. The possible values of this bit are:

0: SYSRESETREQ functionality is available to both Security states.
1: SYSRESETREQ functionality is only available to Secure state.

This bit is RAZ/WI from Non-secure state. This bit resets to zero on a Warm reset

pub fn set_sysresetreq(&mut self, value: bool)

System Reset Request:

0 do not request a reset.
1 request reset.

Writing 1 to this bit asserts a signal to request a reset by the external system. The system components that are reset by this request are IMPLEMENTATION DEFINED. A Local reset is required as part of a system reset request.

A Local reset clears this bit to 0.

See Reset management on page B1-208 for more information

pub fn set_vectclractive(&mut self, value: bool)

Clears all active state information for fixed and configurable exceptions:

0: do not clear state information.
1: clear state information.

The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.

pub fn set_vectreset(&mut self, value: bool)

Writing 1 to this bit causes a local system reset, see Reset management on page B1-559 for more information. This bit self-clears.

The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.

When the processor is halted in Debug state, if a write to the register writes a 1 to both VECTRESET and SYSRESETREQ, the behavior is UNPREDICTABLE.

This bit is write only.

impl Aircr

pub fn vectkey(&mut self)

Must be called before writing the register.

pub fn vectkeystat(&self) -> bool

Verifies that the vector key is correct (see Aircr::vectkey)

Trait Implementations

impl<T> BitRange<T> for Aircrwhere
    u32: BitRange<T>,

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

impl<T> BitRangeMut<T> for Aircrwhere
    u32: BitRangeMut<T>,

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Clone for Aircr

fn clone(&self) -> Aircr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Aircr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<Aircr> for u32

fn from(value: Aircr) -> Self

Converts to this type from the input type.

impl From<u32> for Aircr

fn from(value: u32) -> Self

Converts to this type from the input type.

impl MemoryMappedRegister for Aircr

const ADDRESS: u64 = 3_758_157_068u64

The register’s address in the target memory.

const NAME: &'static str = "AIRCR"

The register’s name.

impl Copy for Aircr