Enum probe_rs::SpecificCoreState
source · [−]pub enum SpecificCoreState {
Armv6m(CortexMState),
Armv7a(CortexAState),
Armv7m(CortexMState),
Armv7em(CortexMState),
Armv8a(CortexAState),
Armv8m(CortexMState),
Riscv(RiscVState),
}
Expand description
The architecture specific core state.
Variants
Armv6m(CortexMState)
The state of an ARMv6-M core.
Armv7a(CortexAState)
The state of an ARMv7-A core.
Armv7m(CortexMState)
The state of an ARMv7-M core.
Armv7em(CortexMState)
The state of an ARMv7-EM core.
Armv8a(CortexAState)
The state of an ARMv8-A core.
Armv8m(CortexMState)
The state of an ARMv8-M core.
Riscv(RiscVState)
The state of an RISC-V core.
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for SpecificCoreState
impl Send for SpecificCoreState
impl Sync for SpecificCoreState
impl Unpin for SpecificCoreState
impl UnwindSafe for SpecificCoreState
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more