Struct probe_rs::architecture::arm::ap::CSW

pub struct CSW {

    pub DbgSwEnable: u8,
    pub HNONSEC: u8,
    pub PROT: u8,
    pub CACHE: u8,
    pub SPIDEN: u8,
    pub _RES0: u8,
    pub MTE: u8,
    pub Type: u8,
    pub Mode: u8,
    pub TrinProg: u8,
    pub DeviceEn: u8,
    pub AddrInc: AddressIncrement,
    pub _RES1: u8,
    pub SIZE: DataSize,
}

Control and Status Word register

The control and status word register (CSW) is used to configure memory access through the memory AP.

Fields

DbgSwEnable: u8

Is debug software access enabled.

HNONSEC: u8

Specifies whether HNONSEC is enabled.

PROT: u8

Prot

CACHE: u8

Cache

SPIDEN: u8

Secure Debug Enabled. This field has one of the following values:

• 0b0 Secure access is disabled.
• 0b1 Secure access is enabled. This field is optional, and read-only. If not implemented, the bit is RES0. If CSW.DEVICEEN is 0b0, SDEVICEEN is ignored and the effective value of SDEVICEEN is 0b1. For more information, see Enabling access to the connected debug device or memory system on page C2-154. Note In ADIv5 and older versions of the architecture, the CSW.SPIDEN field is in the same bit position as CSW.SDeviceEn, and has the same meaning. From ADIv6, the name SDeviceEn is used to avoid confusion between this field and the SPIDEN signal on the authentication interface.

_RES0: u8

Reserved.

MTE: u8

1 if memory tagging access is enabled.

Type: u8

Memory tagging type. Implementation defined.

Mode: u8

Mode of operation. Is set to 0b0000 normally.

TrinProg: u8

A transfer is in progress. Can be used to poll whether an aborted transaction has completed. Read only.

DeviceEn: u8

1 if transactions can be issued through this access port at the moment. Read only.

AddrInc: AddressIncrement

The address increment on DRW access.

_RES1: u8

Reserved

SIZE: DataSize

The access size of this memory AP.

Implementations

impl CSW

pub fn new(data_size: DataSize) -> Self

Creates a new CSW content with default values and a configurable DataSize. See in code documentation for more info.

The CSW Register is set for an AMBA AHB Acccess, according to the ARM Debug Interface Architecture Specification.

The PROT bits are set as follows:

HNONSEC[30] = 1 - Should be One, if not supported.
MasterType, bit [29] = 1 - Access as default AHB Master
HPROT[4] = 0 - Non-allocating access

The CACHE bits are set for the following AHB access:

HPROT[0] == 1 - data access
HPROT[1] == 1 - privileged access
HPROT[2] == 0 - non-cacheable access
HPROT[3] == 0 - non-bufferable access

Trait Implementations

impl Clone for CSW

fn clone(&self) -> CSW

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CSW

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for CSW

fn default() -> CSW

Returns the “default value” for a type.

impl From<CSW> for u32

fn from(value: CSW) -> u32

Converts to this type from the input type.

impl From<u32> for CSW

fn from(value: u32) -> CSW

Converts to this type from the input type.

impl PartialEq<CSW> for CSW

fn eq(&self, other: &CSW) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &CSW) -> bool

This method tests for !=.

impl Register for CSW

const ADDRESS: u8 = 0u8

The address of the register (in bytes).

const NAME: &'static str = _

The name of the register as string.

impl ApRegister<MemoryAp> for CSW

impl Copy for CSW

impl StructuralPartialEq for CSW