#[non_exhaustive]#[repr(u16)]pub enum Opcode {
Show 509 variants
Illegal = 65_535,
Tdi = 0,
Twi = 1,
DcbzL = 2,
PsqLux = 3,
PsqLx = 4,
PsqStux = 5,
PsqStx = 6,
PsAbs = 7,
PsAdd = 8,
PsCmpo0 = 9,
PsCmpo1 = 10,
PsCmpu0 = 11,
PsCmpu1 = 12,
PsDiv = 13,
PsMadd = 14,
PsMadds0 = 15,
PsMadds1 = 16,
PsMerge00 = 17,
PsMerge01 = 18,
PsMerge10 = 19,
PsMerge11 = 20,
PsMr = 21,
PsMsub = 22,
PsMul = 23,
PsMuls0 = 24,
PsMuls1 = 25,
PsNabs = 26,
PsNeg = 27,
PsNmadd = 28,
PsNmsub = 29,
PsRes = 30,
PsRsqrte = 31,
PsSel = 32,
PsSub = 33,
PsSum0 = 34,
PsSum1 = 35,
Mfvscr = 36,
Mtvscr = 37,
Vaddcuw = 38,
Vaddfp = 39,
Vaddsbs = 40,
Vaddshs = 41,
Vaddsws = 42,
Vaddubm = 43,
Vaddubs = 44,
Vadduhm = 45,
Vadduhs = 46,
Vadduwm = 47,
Vadduws = 48,
Vand = 49,
Vandc = 50,
Vavgsb = 51,
Vavgsh = 52,
Vavgsw = 53,
Vavgub = 54,
Vavguh = 55,
Vavguw = 56,
Vcfsx = 57,
Vcfux = 58,
Vcmpbfp = 59,
Vcmpeqfp = 60,
Vcmpequb = 61,
Vcmpequh = 62,
Vcmpequw = 63,
Vcmpgefp = 64,
Vcmpgtfp = 65,
Vcmpgtsb = 66,
Vcmpgtsh = 67,
Vcmpgtsw = 68,
Vcmpgtub = 69,
Vcmpgtuh = 70,
Vcmpgtuw = 71,
Vctsxs = 72,
Vctuxs = 73,
Vexptefp = 74,
Vlogefp = 75,
Vmaddfp = 76,
Vmaxfp = 77,
Vmaxsb = 78,
Vmaxsh = 79,
Vmaxsw = 80,
Vmaxub = 81,
Vmaxuh = 82,
Vmaxuw = 83,
Vmhaddshs = 84,
Vmhraddshs = 85,
Vminfp = 86,
Vminsb = 87,
Vminsh = 88,
Vminsw = 89,
Vminub = 90,
Vminuh = 91,
Vminuw = 92,
Vmladduhm = 93,
Vmrghb = 94,
Vmrghh = 95,
Vmrghw = 96,
Vmrglb = 97,
Vmrglh = 98,
Vmrglw = 99,
Vmsummbm = 100,
Vmsumshm = 101,
Vmsumshs = 102,
Vmsumubm = 103,
Vmsumuhm = 104,
Vmsumuhs = 105,
Vmulesb = 106,
Vmulesh = 107,
Vmuleub = 108,
Vmuleuh = 109,
Vmulosb = 110,
Vmulosh = 111,
Vmuloub = 112,
Vmulouh = 113,
Vnmsubfp = 114,
Vnor = 115,
Vor = 116,
Vperm = 117,
Vpkpx = 118,
Vpkshss = 119,
Vpkshus = 120,
Vpkswss = 121,
Vpkswus = 122,
Vpkuhum = 123,
Vpkuhus = 124,
Vpkuwum = 125,
Vpkuwus = 126,
Vrefp = 127,
Vrfim = 128,
Vrfin = 129,
Vrfip = 130,
Vrfiz = 131,
Vrlb = 132,
Vrlh = 133,
Vrlw = 134,
Vrsqrtefp = 135,
Vsel = 136,
Vsl = 137,
Vslb = 138,
Vsldoi = 139,
Vslh = 140,
Vslo = 141,
Vslw = 142,
Vspltb = 143,
Vsplth = 144,
Vspltisb = 145,
Vspltish = 146,
Vspltisw = 147,
Vspltw = 148,
Vsr = 149,
Vsrab = 150,
Vsrah = 151,
Vsraw = 152,
Vsrb = 153,
Vsrh = 154,
Vsro = 155,
Vsrw = 156,
Vsubcuw = 157,
Vsubfp = 158,
Vsubsbs = 159,
Vsubshs = 160,
Vsubsws = 161,
Vsububm = 162,
Vsububs = 163,
Vsubuhm = 164,
Vsubuhs = 165,
Vsubuwm = 166,
Vsubuws = 167,
Vsumsws = 168,
Vsum2sws = 169,
Vsum4sbs = 170,
Vsum4shs = 171,
Vsum4ubs = 172,
Vupkhpx = 173,
Vupkhsb = 174,
Vupkhsh = 175,
Vupklpx = 176,
Vupklsb = 177,
Vupklsh = 178,
Vxor = 179,
Lvewx128 = 180,
Lvlx128 = 181,
Lvlxl128 = 182,
Lvrx128 = 183,
Lvrxl128 = 184,
Lvsl128 = 185,
Lvsr128 = 186,
Lvx128 = 187,
Lvxl128 = 188,
Stvewx128 = 189,
Stvlx128 = 190,
Stvlxl128 = 191,
Stvrx128 = 192,
Stvrxl128 = 193,
Stvx128 = 194,
Stvxl128 = 195,
Vsldoi128 = 196,
Vaddfp128 = 197,
Vand128 = 198,
Vandc128 = 199,
Vmaddcfp128 = 200,
Vmaddfp128 = 201,
Vmsum3fp128 = 202,
Vmsum4fp128 = 203,
Vmulfp128 = 204,
Vnmsubfp128 = 205,
Vnor128 = 206,
Vor128 = 207,
Vperm128 = 208,
Vpkshss128 = 209,
Vpkshus128 = 210,
Vpkswss128 = 211,
Vpkswus128 = 212,
Vpkuhum128 = 213,
Vpkuhus128 = 214,
Vpkuwum128 = 215,
Vpkuwus128 = 216,
Vsel128 = 217,
Vslo128 = 218,
Vsro128 = 219,
Vsubfp128 = 220,
Vxor128 = 221,
Vctsxs128 = 222,
Vctuxs128 = 223,
Vcmpbfp128 = 224,
Vcmpeqfp128 = 225,
Vcmpequw128 = 226,
Vcmpgefp128 = 227,
Vcmpgtfp128 = 228,
Vcfsx128 = 229,
Vcfux128 = 230,
Vexptefp128 = 231,
Vlogefp128 = 232,
Vmaxfp128 = 233,
Vminfp128 = 234,
Vmrghw128 = 235,
Vmrglw128 = 236,
Vpermwi128 = 237,
Vpkd3d128 = 238,
Vrefp128 = 239,
Vrfim128 = 240,
Vrfin128 = 241,
Vrfip128 = 242,
Vrfiz128 = 243,
Vrlimi128 = 244,
Vrlw128 = 245,
Vrsqrtefp128 = 246,
Vslw128 = 247,
Vspltisw128 = 248,
Vspltw128 = 249,
Vsraw128 = 250,
Vsrw128 = 251,
Vupkd3d128 = 252,
Vupkhsb128 = 253,
Vupkhsh128 = 254,
Vupklsb128 = 255,
Vupklsh128 = 256,
Mulli = 257,
Subfic = 258,
Cmpli = 259,
Cmpi = 260,
Addic = 261,
Addic_ = 262,
Addi = 263,
Addis = 264,
Bc = 265,
Sc = 266,
B = 267,
Bcctr = 268,
Bclr = 269,
Crand = 270,
Crandc = 271,
Creqv = 272,
Crnand = 273,
Crnor = 274,
Cror = 275,
Crorc = 276,
Crxor = 277,
Isync = 278,
Mcrf = 279,
Rfi = 280,
Rfid = 281,
Rlwimi = 282,
Rlwinm = 283,
Rlwnm = 284,
Ori = 285,
Oris = 286,
Xori = 287,
Xoris = 288,
Andi_ = 289,
Andis_ = 290,
Rldcl = 291,
Rldcr = 292,
Rldic = 293,
Rldicl = 294,
Rldicr = 295,
Rldimi = 296,
Add = 297,
Addc = 298,
Adde = 299,
Addme = 300,
Addze = 301,
And = 302,
Andc = 303,
Cmp = 304,
Cmpl = 305,
Cntlzw = 306,
Dcbf = 307,
Dcbi = 308,
Dcbst = 309,
Dcbt = 310,
Dcbtst = 311,
Dcbz = 312,
Divw = 313,
Divwu = 314,
Eciwx = 315,
Ecowx = 316,
Eieio = 317,
Eqv = 318,
Extsb = 319,
Extsh = 320,
Icbi = 321,
Lbzux = 322,
Lbzx = 323,
Lfdux = 324,
Lfdx = 325,
Lfsux = 326,
Lfsx = 327,
Lhaux = 328,
Lhax = 329,
Lhbrx = 330,
Lhzux = 331,
Lhzx = 332,
Lswi = 333,
Lswx = 334,
Lwarx = 335,
Lwbrx = 336,
Lwzux = 337,
Lwzx = 338,
Mcrxr = 339,
Mfcr = 340,
Mfmsr = 341,
Mfspr = 342,
Mfsr = 343,
Mfsrin = 344,
Mftb = 345,
Mtcrf = 346,
Mtmsr = 347,
Mtspr = 348,
Mtsr = 349,
Mtsrin = 350,
Mulhw = 351,
Mulhwu = 352,
Mullw = 353,
Nand = 354,
Neg = 355,
Nor = 356,
Or = 357,
Orc = 358,
Slw = 359,
Sraw = 360,
Srawi = 361,
Srw = 362,
Stbux = 363,
Stbx = 364,
Stfdux = 365,
Stfdx = 366,
Stfiwx = 367,
Stfsux = 368,
Stfsx = 369,
Sthbrx = 370,
Sthux = 371,
Sthx = 372,
Stswi = 373,
Stswx = 374,
Stwbrx = 375,
Stwcx_ = 376,
Stwux = 377,
Stwx = 378,
Subf = 379,
Subfc = 380,
Subfe = 381,
Subfme = 382,
Subfze = 383,
Sync = 384,
Tlbie = 385,
Tlbsync = 386,
Tw = 387,
Xor = 388,
Cntlzd = 389,
Dcbzl = 390,
Divd = 391,
Divdu = 392,
Extsw = 393,
Ldarx = 394,
Ldux = 395,
Ldx = 396,
Lwaux = 397,
Lwax = 398,
Mtmsrd = 399,
Mtsrd = 400,
Mtsrdin = 401,
Mulhd = 402,
Mulhdu = 403,
Mulld = 404,
Slbia = 405,
Slbie = 406,
Sld = 407,
Srad = 408,
Sradi = 409,
Srd = 410,
Stdcx_ = 411,
Stdux = 412,
Stdx = 413,
Td = 414,
Dss = 415,
Dst = 416,
Dstst = 417,
Lvebx = 418,
Lvehx = 419,
Lvewx = 420,
Lvlx = 421,
Lvlxl = 422,
Lvrx = 423,
Lvrxl = 424,
Lvsl = 425,
Lvsr = 426,
Lvx = 427,
Lvxl = 428,
Stvebx = 429,
Stvehx = 430,
Stvewx = 431,
Stvlx = 432,
Stvlxl = 433,
Stvrx = 434,
Stvrxl = 435,
Stvx = 436,
Stvxl = 437,
Lwz = 438,
Lwzu = 439,
Lbz = 440,
Lbzu = 441,
Stw = 442,
Stwu = 443,
Stb = 444,
Stbu = 445,
Lhz = 446,
Lhzu = 447,
Lha = 448,
Lhau = 449,
Sth = 450,
Sthu = 451,
Lmw = 452,
Stmw = 453,
Lfs = 454,
Lfsu = 455,
Lfd = 456,
Lfdu = 457,
Stfs = 458,
Stfsu = 459,
Stfd = 460,
Stfdu = 461,
PsqL = 462,
PsqLu = 463,
Ld = 464,
Ldu = 465,
Lwa = 466,
Fadds = 467,
Fdivs = 468,
Fmadds = 469,
Fmsubs = 470,
Fmuls = 471,
Fnmadds = 472,
Fnmsubs = 473,
Fres = 474,
Fsubs = 475,
PsqSt = 476,
PsqStu = 477,
Std = 478,
Stdu = 479,
Fabs = 480,
Fadd = 481,
Fcmpo = 482,
Fcmpu = 483,
Fctiw = 484,
Fctiwz = 485,
Fdiv = 486,
Fmadd = 487,
Fmr = 488,
Fmsub = 489,
Fmul = 490,
Fnabs = 491,
Fneg = 492,
Fnmadd = 493,
Fnmsub = 494,
Frsp = 495,
Frsqrte = 496,
Fsel = 497,
Fsub = 498,
Mcrfs = 499,
Mffs = 500,
Mtfsb0 = 501,
Mtfsb1 = 502,
Mtfsf = 503,
Mtfsfi = 504,
Fcfid = 505,
Fctid = 506,
Fctidz = 507,
}Variants (Non-exhaustive)§
This enum is marked as non-exhaustive
Illegal = 65_535
An illegal or unknown opcode
Tdi = 0
tdi: Trap Double Word Immediate
Twi = 1
twi: Trap Word Immediate
DcbzL = 2
dcbz_l: Data Cache Block Set to Zero Locked
PsqLux = 3
psq_lux: Paired Single Quantized Load with Update Indexed
PsqLx = 4
psq_lx: Paired Single Quantized Load Indexed
PsqStux = 5
psq_stux: Paired Single Quantized Store with Update Indexed
PsqStx = 6
psq_stx: Paired Single Quantized Store Indexed
PsAbs = 7
ps_abs: Paired Single Absolute Value
PsAdd = 8
ps_add: Paired Single Add
PsCmpo0 = 9
ps_cmpo0: Paired Singles Compare Ordered High
PsCmpo1 = 10
ps_cmpo1: Paired Singles Compare Ordered Low
PsCmpu0 = 11
ps_cmpu0: Paired Singles Compare Unordered High
PsCmpu1 = 12
ps_cmpu1: Paired Singles Compare Unordered Low
PsDiv = 13
ps_div: Paired Single Divide
PsMadd = 14
ps_madd: Paired Single Multiply-Add
PsMadds0 = 15
ps_madds0: Paired Single Multiply-Add Scalar high
PsMadds1 = 16
ps_madds1: Paired Single Multiply-Add Scalar low
PsMerge00 = 17
ps_merge00: Paired Single MERGE high
PsMerge01 = 18
ps_merge01: Paired Single MERGE direct
PsMerge10 = 19
ps_merge10: Paired Single MERGE swapped
PsMerge11 = 20
ps_merge11: Paired Single MERGE low
PsMr = 21
ps_mr: Paired Single Move Register
PsMsub = 22
ps_msub: Paired Single Multiply-Subtract
PsMul = 23
ps_mul: Paired Single Multiply
PsMuls0 = 24
ps_muls0: Paired Single Multiply Scalar high
PsMuls1 = 25
ps_muls1: Paired Single Multiply Scalar low
PsNabs = 26
ps_nabs: Paired Single Negative Absolute Value
PsNeg = 27
ps_neg: Paired Single Negate
PsNmadd = 28
ps_nmadd: Paired Single Negative Multiply-Add
PsNmsub = 29
ps_nmsub: Paired Single Negative Multiply-Subtract
PsRes = 30
ps_res: Paired Single Reciprocal Estimate
PsRsqrte = 31
ps_rsqrte: Paired Single Reciprocal Square Root Estimate
PsSel = 32
ps_sel: Paired Single Select
PsSub = 33
ps_sub: Paired Single Subtract
PsSum0 = 34
ps_sum0: Paired Single vector SUM high
PsSum1 = 35
ps_sum1: Paired Single vector SUM low
Mfvscr = 36
mfvscr: Move from Vector Status and Control Register
Mtvscr = 37
mtvscr: Move to Vector Status and Control Register
Vaddcuw = 38
vaddcuw: Vector Add Carryout Unsigned Word
Vaddfp = 39
vaddfp: Vector Add Floating Point
Vaddsbs = 40
vaddsbs: Vector Add Signed Byte Saturate
Vaddshs = 41
vaddshs: Vector Add Signed Half Word Saturate
Vaddsws = 42
vaddsws: Vector Add Signed Word Saturate
Vaddubm = 43
vaddubm: Vector Add Unsigned Byte Modulo
Vaddubs = 44
vaddubs: Vector Add Unsigned Byte Saturate
Vadduhm = 45
vadduhm: Vector Add Unsigned Half Word Modulo
Vadduhs = 46
vadduhs: Vector Add Unsigned Half Word Saturate
Vadduwm = 47
vadduwm: Vector Add Unsigned Word Modulo
Vadduws = 48
vadduws: Vector Add Unsigned Word Saturate
Vand = 49
vand: Vector Logical AND
Vandc = 50
vandc: Vector Logical AND with Complement
Vavgsb = 51
vavgsb: Vector Average Signed Byte
Vavgsh = 52
vavgsh: Vector Average Signed Half Word
Vavgsw = 53
vavgsw: Vector Average Signed Word
Vavgub = 54
vavgub: Vector Average Unsigned Byte
Vavguh = 55
vavguh: Vector Average Unsigned Half Word
Vavguw = 56
vavguw: Vector Average Unsigned Word
Vcfsx = 57
vcfsx: Vector Convert from Signed Fixed-Point Word
Vcfux = 58
vcfux: Vector Convert from Unsigned Fixed-Point Word
Vcmpbfp = 59
vcmpbfp: Vector Compare Bounds Floating Point
Vcmpeqfp = 60
vcmpeqfp: Vector Compare Equal-to-Floating Point
Vcmpequb = 61
vcmpequb: Vector Compare Equal-to Unsigned Byte
Vcmpequh = 62
vcmpequh: Vector Compare Equal-to Unsigned Half Word
Vcmpequw = 63
vcmpequw: Vector Compare Equal-to Unsigned Word
Vcmpgefp = 64
vcmpgefp: Vector Compare Greater-Than-or-Equal-to Floating Point
Vcmpgtfp = 65
vcmpgtfp: Vector Compare Greater-Than Floating Point
Vcmpgtsb = 66
vcmpgtsb: Vector Compare Greater-Than Signed Byte
Vcmpgtsh = 67
vcmpgtsh: Vector Compare Greater-Than Condition Register Signed Half Word
Vcmpgtsw = 68
vcmpgtsw: Vector Compare Greater-Than Signed Word
Vcmpgtub = 69
vcmpgtub: Vector Compare Greater-Than Unsigned Byte
Vcmpgtuh = 70
vcmpgtuh: Vector Compare Greater-Than Unsigned Half Word
Vcmpgtuw = 71
vcmpgtuw: Vector Compare Greater-Than Unsigned Word
Vctsxs = 72
vctsxs: Vector Convert to Signed Fixed-Point Word Saturate
Vctuxs = 73
vctuxs: Vector Convert to Unsigned Fixed-Point Word Saturate
Vexptefp = 74
vexptefp: Vector 2 Raised to the Exponent Estimate Floating Point
Vlogefp = 75
vlogefp: Vector Log2 Estimate Floating Point
Vmaddfp = 76
vmaddfp: Vector Multiply Add Floating Point
Vmaxfp = 77
vmaxfp: Vector Maximum Floating Point
Vmaxsb = 78
vmaxsb: Vector Maximum Signed Byte
Vmaxsh = 79
vmaxsh: Vector Maximum Signed Half Word
Vmaxsw = 80
vmaxsw: Vector Maximum Signed Word
Vmaxub = 81
vmaxub: Vector Maximum Unsigned Byte
Vmaxuh = 82
vmaxuh: Vector Maximum Unsigned Half Word
Vmaxuw = 83
vmaxuw: Vector Maximum Unsigned Word
Vmhaddshs = 84
vmhaddshs: Vector Multiply High and Add Signed Half Word Saturate
Vmhraddshs = 85
vmhraddshs: Vector Multiply High Round and Add Signed Half Word Saturate
Vminfp = 86
vminfp: Vector Minimum Floating Point
Vminsb = 87
vminsb: Vector Minimum Signed Byte
Vminsh = 88
vminsh: Vector Minimum Signed Half Word
Vminsw = 89
vminsw: Vector Minimum Signed Word
Vminub = 90
vminub: Vector Minimum Unsigned Byte
Vminuh = 91
vminuh: Vector Minimum Unsigned Half Word
Vminuw = 92
vminuw: Vector Minimum Unsigned Word
Vmladduhm = 93
vmladduhm: Vector Multiply Low and Add Unsigned Half Word Modulo
Vmrghb = 94
vmrghb: Vector Merge High Byte
Vmrghh = 95
vmrghh: Vector Merge High Half Word
Vmrghw = 96
vmrghw: Vector Merge High Word
Vmrglb = 97
vmrglb: Vector Merge Low Byte
Vmrglh = 98
vmrglh: Vector Merge Low Half Word
Vmrglw = 99
vmrglw: Vector Merge Low Word
Vmsummbm = 100
vmsummbm: Vector Multiply Sum Mixed-Sign Byte Modulo
Vmsumshm = 101
vmsumshm: Vector Multiply Sum Signed Half Word Modulo
Vmsumshs = 102
vmsumshs: Vector Multiply Sum Signed Half Word Saturate
Vmsumubm = 103
vmsumubm: Vector Multiply Sum Unsigned Byte Modulo
Vmsumuhm = 104
vmsumuhm: Vector Multiply Sum Unsigned Half Word Modulo
Vmsumuhs = 105
vmsumuhs: Vector Multiply Sum Unsigned Half Word Saturate
Vmulesb = 106
vmulesb: Vector Multiply Even Signed Byte
Vmulesh = 107
vmulesh: Vector Multiply Even Signed Half Word
Vmuleub = 108
vmuleub: Vector Multiply Even Unsigned Byte
Vmuleuh = 109
vmuleuh: Vector Multiply Even Unsigned Half Word
Vmulosb = 110
vmulosb: Vector Multiply Odd Signed Byte
Vmulosh = 111
vmulosh: Vector Multiply Odd Signed Half Word
Vmuloub = 112
vmuloub: Vector Multiply Odd Unsigned Byte
Vmulouh = 113
vmulouh: Vector Multiply Odd Unsigned Half Word
Vnmsubfp = 114
vnmsubfp: Vector Negative Multiply-Subtract Floating Point
Vnor = 115
vnor: Vector Logical NOR
Vor = 116
vor: Vector Logical OR
Vperm = 117
vperm: Vector Permute
Vpkpx = 118
vpkpx: Vector Pack Pixel32
Vpkshss = 119
vpkshss: Vector Pack Signed Half Word Signed Saturate
Vpkshus = 120
vpkshus: Vector Pack Signed Half Word Unsigned Saturate
Vpkswss = 121
vpkswss: Vector Pack Signed Word Signed Saturate
Vpkswus = 122
vpkswus: Vector Pack Signed Word Unsigned Saturate
Vpkuhum = 123
vpkuhum: Vector Pack Unsigned Half Word Unsigned Modulo
Vpkuhus = 124
vpkuhus: Vector Pack Unsigned Half Word Unsigned Saturate
Vpkuwum = 125
vpkuwum: Vector Pack Unsigned Word Unsigned Modulo
Vpkuwus = 126
vpkuwus: Vector Pack Unsigned Word Unsigned Saturate
Vrefp = 127
vrefp: Vector Reciprocal Estimate Floating Point
Vrfim = 128
vrfim: Vector Round to Floating-Point Integer toward Minus Infinity
Vrfin = 129
vrfin: Vector Round to Floating-Point Integer Nearest
Vrfip = 130
vrfip: Vector Round to Floating-Point Integer toward Plus Infinity
Vrfiz = 131
vrfiz: Vector Round to Floating-Point Integer toward Zero
Vrlb = 132
vrlb: Vector Rotate Left Integer Byte
Vrlh = 133
vrlh: Vector Rotate Left Integer Half Word
Vrlw = 134
vrlw: Vector Rotate Left Integer Word
Vrsqrtefp = 135
vrsqrtefp: Vector Reciprocal Square Root Estimate Floating Point
Vsel = 136
vsel: Vector Conditional Select
Vsl = 137
vsl: Vector Shift Left
Vslb = 138
vslb: Vector Shift Left Integer Byte
Vsldoi = 139
vsldoi: Vector Shift Left Double by Octet Immediate
Vslh = 140
vslh: Vector Shift Left Integer Half Word
Vslo = 141
vslo: Vector Shift Left by Octet
Vslw = 142
vslw: Vector Shift Left Integer Word
Vspltb = 143
vspltb: Vector Splat Byte
Vsplth = 144
vsplth: Vector Splat Half Word
Vspltisb = 145
vspltisb: Vector Splat Immediate Signed Byte
Vspltish = 146
vspltish: Vector Splat Immediate Signed Half Word
Vspltisw = 147
vspltisw: Vector Splat Immediate Signed Word
Vspltw = 148
vspltw: Vector Splat Word
Vsr = 149
vsr: Vector Shift Right
Vsrab = 150
vsrab: Vector Shift Right Algebraic Byte
Vsrah = 151
vsrah: Vector Shift Right Algebraic Half Word
Vsraw = 152
vsraw: Vector Shift Right Algebraic Word
Vsrb = 153
vsrb: Vector Shift Right Byte
Vsrh = 154
vsrh: Vector Shift Right Half Word
Vsro = 155
vsro: Vector Shift Right by Octet
Vsrw = 156
vsrw: Vector Shift Right Word
Vsubcuw = 157
vsubcuw: Vector Subtract Carryout Unsigned Word
Vsubfp = 158
vsubfp: Vector Subtract Floating Point
Vsubsbs = 159
vsubsbs: Vector Subtract Signed Byte Saturate
Vsubshs = 160
vsubshs: Vector Subtract Signed Half Word Saturate
Vsubsws = 161
vsubsws: Vector Subtract Signed Word Saturate
Vsububm = 162
vsububm: Vector Subtract Unsigned Byte Modulo
Vsububs = 163
vsububs: Vector Subtract Unsigned Byte Saturate
Vsubuhm = 164
vsubuhm: Vector Subtract Unsigned Half Word Modulo
Vsubuhs = 165
vsubuhs: Vector Subtract Unsigned Half Word Saturate
Vsubuwm = 166
vsubuwm: Vector Subtract Unsigned Word Modulo
Vsubuws = 167
vsubuws: Vector Subtract Unsigned Word Saturate
Vsumsws = 168
vsumsws: Vector Sum Across Signed Word Saturate
Vsum2sws = 169
vsum2sws: Vector Sum Across Partial (1/2) Signed Word Saturate
Vsum4sbs = 170
vsum4sbs: Vector Sum Across Partial (1/4) Signed Byte Saturate
Vsum4shs = 171
vsum4shs: Vector Sum Across Partial (1/4) Signed Half Word Saturate
Vsum4ubs = 172
vsum4ubs: Vector Sum Across Partial (1/4) Unsigned Byte Saturate
Vupkhpx = 173
vupkhpx: Vector Unpack High Pixel16
Vupkhsb = 174
vupkhsb: Vector Unpack High Signed Byte
Vupkhsh = 175
vupkhsh: Vector Unpack High Signed Half Word
Vupklpx = 176
vupklpx: Vector Unpack Low Pixel16
Vupklsb = 177
vupklsb: Vector Unpack Low Signed Byte
Vupklsh = 178
vupklsh: Vector Unpack Low Signed Half Word
Vxor = 179
vxor: Vector Logical XOR
Lvewx128 = 180
lvewx128: Load Vector128 Element Word Indexed
Lvlx128 = 181
lvlx128: Load Vector128 Left Indexed
Lvlxl128 = 182
lvlxl128: Load Vector128 Left Indexed LRU
Lvrx128 = 183
lvrx128: Load Vector128 Right Indexed
Lvrxl128 = 184
lvrxl128: Load Vector128 Right Indexed LRU
Lvsl128 = 185
lvsl128: Load Vector128 for Shift Left
Lvsr128 = 186
lvsr128: Load Vector128 for Shift Right
Lvx128 = 187
lvx128: Load Vector128 Indexed
Lvxl128 = 188
lvxl128: Load Vector128 Indexed LRU
Stvewx128 = 189
stvewx128: Store Vector128 Element Word Indexed
Stvlx128 = 190
stvlx128: Store Vector128 Left Indexed
Stvlxl128 = 191
stvlxl128: Store Vector128 Left Indexed LRU
Stvrx128 = 192
stvrx128: Store Vector128 Right Indexed
Stvrxl128 = 193
stvrxl128: Store Vector128 Right Indexed LRU
Stvx128 = 194
stvx128: Store Vector128 Indexed
Stvxl128 = 195
stvxl128: Store Vector128 Indexed LRU
Vsldoi128 = 196
vsldoi128: Vector128 Shift Left Double by Octet Immediate
Vaddfp128 = 197
vaddfp128: Vector128 Add Floating Point
Vand128 = 198
vand128: Vector128 Logical AND
Vandc128 = 199
vandc128: Vector128 Logical AND with Complement
Vmaddcfp128 = 200
vmaddcfp128: Vector128 Multiply Add Carryout Floating Point
Vmaddfp128 = 201
vmaddfp128: Vector128 Multiply Add Floating Point
Vmsum3fp128 = 202
vmsum3fp128: Vector128 Multiply Sum 3-way Floating Point
Vmsum4fp128 = 203
vmsum4fp128: Vector128 Multiply Sum 4-way Floating Point
Vmulfp128 = 204
vmulfp128: Vector128 Multiply Floating-Point
Vnmsubfp128 = 205
vnmsubfp128: Vector128 Negative Multiply-Subtract Floating Point
Vnor128 = 206
vnor128: Vector128 Logical NOR
Vor128 = 207
vor128: Vector128 Logical OR
Vperm128 = 208
vperm128: Vector128 Permutation
Vpkshss128 = 209
vpkshss128: Vector128 Pack Signed Half Word Signed Saturate
Vpkshus128 = 210
vpkshus128: Vector128 Pack Signed Half Word Unsigned Saturate
Vpkswss128 = 211
vpkswss128: Vector128 Pack Signed Word Signed Saturate
Vpkswus128 = 212
vpkswus128: Vector128 Pack Signed Word Unsigned Saturate
Vpkuhum128 = 213
vpkuhum128: Vector128 Pack Unsigned Half Word Unsigned Modulo
Vpkuhus128 = 214
vpkuhus128: Vector128 Pack Unsigned Half Word Unsigned Saturate
Vpkuwum128 = 215
vpkuwum128: Vector128 Pack Unsigned Word Unsigned Modulo
Vpkuwus128 = 216
vpkuwus128: Vector128 Pack Unsigned Word Unsigned Saturate
Vsel128 = 217
vsel128: Vector128 Select
Vslo128 = 218
vslo128: Vector128 Shift Left Octet
Vsro128 = 219
vsro128: Vector128 Shift Right Octet
Vsubfp128 = 220
vsubfp128: Vector128 Subtract Floating Point
Vxor128 = 221
vxor128: Vector128 Logical XOR
Vctsxs128 = 222
vctsxs128: Vector128 Convert to Signed Fixed-Point Word Saturate
Vctuxs128 = 223
vctuxs128: Vector128 Convert to Unsigned Fixed-Point Word Saturate
Vcmpbfp128 = 224
vcmpbfp128: Vector128 Compare Bounds Floating Point
Vcmpeqfp128 = 225
vcmpeqfp128: Vector128 Compare Equal-to Floating Point
Vcmpequw128 = 226
vcmpequw128: Vector128 Compare Equal-to Unsigned Word
Vcmpgefp128 = 227
vcmpgefp128: Vector128 Compare Greater-Than-or-Equal-to Floating Point
Vcmpgtfp128 = 228
vcmpgtfp128: Vector128 Compare Greater-Than Floating-Point
Vcfsx128 = 229
vcfsx128: Vector128 Convert From Signed Fixed-Point Word
Vcfux128 = 230
vcfux128: Vector128 Convert From Unsigned Fixed-Point Word
Vexptefp128 = 231
vexptefp128: Vector128 2 Raised to the Exponent Estimate Floating Point
Vlogefp128 = 232
vlogefp128: Vector128 Log2 Estimate Floating Point
Vmaxfp128 = 233
vmaxfp128: Vector128 Maximum Floating Point
Vminfp128 = 234
vminfp128: Vector128 Minimum Floating Point
Vmrghw128 = 235
vmrghw128: Vector128 Merge High Word
Vmrglw128 = 236
vmrglw128: Vector128 Merge Low Word
Vpermwi128 = 237
vpermwi128: Vector128 Permutate Word Immediate
Vpkd3d128 = 238
vpkd3d128: Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert
Vrefp128 = 239
vrefp128: Vector128 Reciprocal Estimate Floating Point
Vrfim128 = 240
vrfim128: Vector128 Round to Floating-Point Integer toward Minus Infinity
Vrfin128 = 241
vrfin128: Vector128 Round to Floating-Point Integer toward Nearest
Vrfip128 = 242
vrfip128: Vector128 Round to Floating-Point Integer toward Plus Infinity
Vrfiz128 = 243
vrfiz128: Vector128 Round to Floating-Point Integer toward Zero
Vrlimi128 = 244
vrlimi128: Vector128 Rotate Left Immediate and Mask Insert
Vrlw128 = 245
vrlw128: Vector128 Rotate Left Word
Vrsqrtefp128 = 246
vrsqrtefp128: Vector128 Reciprocal Square Root Estimate Floating Point
Vslw128 = 247
vslw128: Vector128 Shift Left Word
Vspltisw128 = 248
vspltisw128: Vector128 Splat Immediate Signed Word
Vspltw128 = 249
vspltw128: Vector128 Splat Word
Vsraw128 = 250
vsraw128: Vector128 Shift Right Arithmetic Word
Vsrw128 = 251
vsrw128: Vector128 Shift Right Word
Vupkd3d128 = 252
vupkd3d128: Vector128 Unpack D3Dtype
Vupkhsb128 = 253
vupkhsb128: Vector128 Unpack High Signed Byte
Vupkhsh128 = 254
vupkhsh128: Vector128 Unpack High Signed Half Word
Vupklsb128 = 255
vupklsb128: Vector128 Unpack Low Signed Byte
Vupklsh128 = 256
vupklsh128: Vector128 Unpack Low Signed Half Word
Mulli = 257
mulli: Multiply Low Immediate
Subfic = 258
subfic: Subtract from Immediate Carrying
Cmpli = 259
cmpli: Compare Logical Immediate
Cmpi = 260
cmpi: Compare Immediate
Addic = 261
addic: Add Immediate Carrying
Addic_ = 262
addic.: Add Immediate Carrying and Record
Addi = 263
addi: Add Immediate
Addis = 264
addis: Add Immediate Shifted
Bc = 265
bc: Branch Conditional
Sc = 266
sc: System Call
B = 267
b: Branch
Bcctr = 268
bcctr: Branch Conditional to Count Register
Bclr = 269
bclr: Branch Conditional to Link Register
Crand = 270
crand: Condition Register AND
Crandc = 271
crandc: Condition Register AND with Complement
Creqv = 272
creqv: Condition Register Equivalent
Crnand = 273
crnand: Condition Register NAND
Crnor = 274
crnor: Condition Register NOR
Cror = 275
cror: Condition Register OR
Crorc = 276
crorc: Condition Register OR with Complement
Crxor = 277
crxor: Condition Register XOR
Isync = 278
isync: Instruction Synchronize
Mcrf = 279
mcrf: Move Condition Register Field
Rfi = 280
rfi: Return from Interrupt
Rfid = 281
rfid: Return from Interrupt Double Word
Rlwimi = 282
rlwimi: Rotate Left Word Immediate then Mask Insert
Rlwinm = 283
rlwinm: Rotate Left Word Immediate then AND with Mask
Rlwnm = 284
rlwnm: Rotate Left Word then AND with Mask
Ori = 285
ori: OR Immediate
Oris = 286
oris: OR Immediate Shifted
Xori = 287
xori: XOR Immediate
Xoris = 288
xoris: XOR Immediate Shifted
Andi_ = 289
andi.: AND Immediate
Andis_ = 290
andis.: AND Immediate Shifted
Rldcl = 291
rldcl: Rotate Left Double Word then Clear Left
Rldcr = 292
rldcr: Rotate Left Double Word then Clear Right
Rldic = 293
rldic: Rotate Left Double Word Immediate then Clear
Rldicl = 294
rldicl: Rotate Left Double Word Immediate then Clear Left
Rldicr = 295
rldicr: Rotate Left Double Word Immediate then Clear Right
Rldimi = 296
rldimi: Rotate Left Double Word Immediate then Mask Insert
Add = 297
add: Add
Addc = 298
addc: Add Carrying
Adde = 299
adde: Add Extended
Addme = 300
addme: Add to Minus One Extended
Addze = 301
addze: Add to Zero Extended
And = 302
and: AND
Andc = 303
andc: AND with Complement
Cmp = 304
cmp: Compare
Cmpl = 305
cmpl: Compare Logical
Cntlzw = 306
cntlzw: Count Leading Zeros Word
Dcbf = 307
dcbf: Data Cache Block Flush
Dcbi = 308
dcbi: Data Cache Block Invalidate
Dcbst = 309
dcbst: Data Cache Block Store
Dcbt = 310
dcbt: Data Cache Block Touch
Dcbtst = 311
dcbtst: Data Cache Block Touch for Store
Dcbz = 312
dcbz: Data Cache Block Clear to Zero
Divw = 313
divw: Divide Word
Divwu = 314
divwu: Divide Word Unsigned
Eciwx = 315
eciwx: External Control In Word Indexed
Ecowx = 316
ecowx: External Control Out Word Indexed
Eieio = 317
eieio: Enforce In-Order Execution of I/O
Eqv = 318
eqv: Equivalent
Extsb = 319
extsb: Extend Sign Byte
Extsh = 320
extsh: Extend Sign Half Word
Icbi = 321
icbi: Instruction Cache Block Invalidate
Lbzux = 322
lbzux: Load Byte and Zero with Update Indexed
Lbzx = 323
lbzx: Load Byte and Zero Indexed
Lfdux = 324
lfdux: Load Floating-Point Double with Update Indexed
Lfdx = 325
lfdx: Load Floating-Point Double Indexed
Lfsux = 326
lfsux: Load Floating-Point Single with Update Indexed
Lfsx = 327
lfsx: Load Floating-Point Single Indexed
Lhaux = 328
lhaux: Load Half Word Algebraic with Update Indexed
Lhax = 329
lhax: Load Half Word Algebraic Indexed
Lhbrx = 330
lhbrx: Load Half Word Byte-Reverse Indexed
Lhzux = 331
lhzux: Load Half Word and Zero with Update Indexed
Lhzx = 332
lhzx: Load Half Word and Zero Indexed
Lswi = 333
lswi: Load String Word Immediate
Lswx = 334
lswx: Load String Word Indexed
Lwarx = 335
lwarx: Load String Word and Reverse Indexed
Lwbrx = 336
lwbrx: Load String Word and Byte-Reverse Indexed
Lwzux = 337
lwzux: Load Word and Zero with Update Indexed
Lwzx = 338
lwzx: Load Word and Zero Indexed
Mcrxr = 339
mcrxr: Move to Condition Register from XER
Mfcr = 340
mfcr: Move from Condition Register
Mfmsr = 341
mfmsr: Move from Machine State Register
Mfspr = 342
mfspr: Move from Special-Purpose Register
Mfsr = 343
mfsr: Move from Segment Register
Mfsrin = 344
mfsrin: Move from Segment Register Indirect
Mftb = 345
mftb: Move from Time Base
Mtcrf = 346
mtcrf: Move to Condition Register Fields
Mtmsr = 347
mtmsr: Move to Machine State Register
Mtspr = 348
mtspr: Move to Special-Purpose Register
Mtsr = 349
mtsr: Move to Segment Register
Mtsrin = 350
mtsrin: Move to Segment Register Indirect
Mulhw = 351
mulhw: Multiply High Word
Mulhwu = 352
mulhwu: Multiply High Word Unsigned
Mullw = 353
mullw: Multiply Low Word
Nand = 354
nand: NAND
Neg = 355
neg: Negate
Nor = 356
nor: NOR
Or = 357
or: OR
Orc = 358
orc: OR with Complement
Slw = 359
slw: Shift Left Word
Sraw = 360
sraw: Shift Right Algebraic Word
Srawi = 361
srawi: Shift Right Algebraic Word Immediate
Srw = 362
srw: Shift Right Word
Stbux = 363
stbux: Store Byte with Update Indexed
Stbx = 364
stbx: Store Byte Indexed
Stfdux = 365
stfdux: Store Floating-Point Double with Update Indexed
Stfdx = 366
stfdx: Store Floating-Point Double Indexed
Stfiwx = 367
stfiwx: Store Floating-Point as Integer Word Indexed
Stfsux = 368
stfsux: Store Floating-Point Single with Update Indexed
Stfsx = 369
stfsx: Store Floating-Point Single Indexed
Sthbrx = 370
sthbrx: Store Half Word Byte-Reverse Indexed
Sthux = 371
sthux: Store Half Word with Update Indexed
Sthx = 372
sthx: Store Half Word Indexed
Stswi = 373
stswi: Store String Word Immediate
Stswx = 374
stswx: Store String Word Indexed
Stwbrx = 375
stwbrx: Store Word Byte-Reverse Indexed
Stwcx_ = 376
stwcx.: Store Word Conditional Indexed
Stwux = 377
stwux: Store Word Indexed
Stwx = 378
stwx: Store Word Indexed
Subf = 379
subf: Subtract From Carrying
Subfc = 380
subfc: Subtract from Carrying
Subfe = 381
subfe: Subtract from Extended
Subfme = 382
subfme: Subtract from Minus One Extended
Subfze = 383
subfze: Subtract from Zero Extended
Sync = 384
sync: Synchronize
Tlbie = 385
tlbie: Translation Lookaside Buffer Invalidate Entry
Tlbsync = 386
tlbsync: TLB Synchronize
Tw = 387
tw: Trap Word
Xor = 388
xor: XOR
Cntlzd = 389
cntlzd: Count Leading Zeros Double Word
Dcbzl = 390
dcbzl: Data Cache Block Clear to Zero (128 bytes)
Divd = 391
divd: Divide Double Word
Divdu = 392
divdu: Divide Double Word Unsigned
Extsw = 393
extsw: Extend Sign Word
Ldarx = 394
ldarx: Load Double Word and Reserve Indexed
Ldux = 395
ldux: Load Double Word with Update Indexed
Ldx = 396
ldx: Load Double Word Indexed
Lwaux = 397
lwaux: Load Word Algebraic with Update Indexed
Lwax = 398
lwax: Load Word Algebraic Indexed
Mtmsrd = 399
mtmsrd: Move to Machine State Register Double Word
Mtsrd = 400
mtsrd: Move to Segment Register Double Word
Mtsrdin = 401
mtsrdin: Move to Segment Register Double Word Indirect
Mulhd = 402
mulhd: Multiply High Double Word
Mulhdu = 403
mulhdu: Multiply High Double Word Unsigned
Mulld = 404
mulld: Multiply Low Double Word
Slbia = 405
slbia: SLB Invalidate All
Slbie = 406
slbie: SLB Invalidate Entry
Sld = 407
sld: Shift Left Double Word
Srad = 408
srad: Shift Right Algebraic Double Word
Sradi = 409
sradi: Shift Right Algebraic Double Word Immediate
Srd = 410
srd: Shift Right Double Word
Stdcx_ = 411
stdcx.: Store Double Word Conditional Indexed
Stdux = 412
stdux: Store Double Word with Update Indexed
Stdx = 413
stdx: Store Double Word Indexed
Td = 414
td: Trap Double Word
Dss = 415
dss: Data Stream Stop
Dst = 416
dst: Data Stream Touch
Dstst = 417
dstst: Data Stream Touch for Store
Lvebx = 418
lvebx: Load Vector Element Byte Indexed
Lvehx = 419
lvehx: Load Vector Element Half Word Indexed
Lvewx = 420
lvewx: Load Vector Element Word Indexed
Lvlx = 421
lvlx: Load Vector Left Indexed
Lvlxl = 422
lvlxl: Load Vector Left Indexed Last
Lvrx = 423
lvrx: Load Vector Right Indexed
Lvrxl = 424
lvrxl: Load Vector Right Indexed Last
Lvsl = 425
lvsl: Load Vector for Shift Left
Lvsr = 426
lvsr: Load Vector for Shift Right
Lvx = 427
lvx: Load Vector Indexed
Lvxl = 428
lvxl: Load Vector Indexed LRU
Stvebx = 429
stvebx: Store Vector Element Byte Indexed
Stvehx = 430
stvehx: Store Vector Element Half Word Indexed
Stvewx = 431
stvewx: Store Vector Element Word Indexed
Stvlx = 432
stvlx: Store Vector Left Indexed
Stvlxl = 433
stvlxl: Store Vector Left Indexed Last
Stvrx = 434
stvrx: Store Vector Right Indexed
Stvrxl = 435
stvrxl: Store Vector Right Indexed Last
Stvx = 436
stvx: Store Vector Indexed
Stvxl = 437
stvxl: Store Vector Indexed LRU
Lwz = 438
lwz: Load Word and Zero
Lwzu = 439
lwzu: Load Word and Zero with Update
Lbz = 440
lbz: Load Byte and Zero
Lbzu = 441
lbzu: Load Byte and Zero with Update
Stw = 442
stw: Store Word
Stwu = 443
stwu: Store Word with Update
Stb = 444
stb: Store Byte
Stbu = 445
stbu: Store Byte with Update
Lhz = 446
lhz: Load Half Word and Zero
Lhzu = 447
lhzu: Load Half Word and Zero with Update
Lha = 448
lha: Load Half Word Algebraic
Lhau = 449
lhau: Load Half Word Algebraic with Update
Sth = 450
sth: Store Half Word
Sthu = 451
sthu: Store Half Word with Update
Lmw = 452
lmw: Load Multiple Word
Stmw = 453
stmw: Store Multiple Word
Lfs = 454
lfs: Load Floating-Point Single
Lfsu = 455
lfsu: Load Floating-Point Single with Update
Lfd = 456
lfd: Load Floating-Point Double
Lfdu = 457
lfdu: Load Floating-Point Double with Update
Stfs = 458
stfs: Store Floating-Point Single
Stfsu = 459
stfsu: Store Floating-Point Single with Update
Stfd = 460
stfd: Store Floating-Point Double
Stfdu = 461
stfdu: Store Floating-Point Double with Update
PsqL = 462
psq_l: Paired Single Quantized Load
PsqLu = 463
psq_lu: Paired Single Quantized Load with Update
Ld = 464
ld: Load Double Word
Ldu = 465
ldu: Load Double Word with Update
Lwa = 466
lwa: Load Word Algebraic
Fadds = 467
fadds: Floating Add (Single-Precision)
Fdivs = 468
fdivs: Floating Divide (Single-Precision)
Fmadds = 469
fmadds: Floating Multiply-Add (Single-Precision)
Fmsubs = 470
fmsubs: Floating Multiply-Subtract (Single-Precision)
Fmuls = 471
fmuls: Floating Multiply (Single-Precision)
Fnmadds = 472
fnmadds: Floating Negative Multiply-Add (Single-Precision)
Fnmsubs = 473
fnmsubs: Floating Negative Multiply-Subtract (Single-Precision)
Fres = 474
fres: Floating Reciprocal Estimate Single
Fsubs = 475
fsubs: Floating Subtract (Single-Precision)
PsqSt = 476
psq_st: Paired Single Quantized Store
PsqStu = 477
psq_stu: Paired Single Quantized Store with Update
Std = 478
std: Store Double Word
Stdu = 479
stdu: Store Double Word with Update
Fabs = 480
fabs: Floating Absolute Value
Fadd = 481
fadd: Floating Add (Double-Precision)
Fcmpo = 482
fcmpo: Floating Compare Ordered
Fcmpu = 483
fcmpu: Floating Compare Unordered
Fctiw = 484
fctiw: Floating Convert to Integer Word
Fctiwz = 485
fctiwz: Floating Convert to Integer Word with Round toward Zero
Fdiv = 486
fdiv: Floating Divide (Double-Precision)
Fmadd = 487
fmadd: Floating Multiply-Add (Double-Precision)
Fmr = 488
fmr: Floating Move Register (Double-Precision)
Fmsub = 489
fmsub: Floating Multiply-Subtract (Double-Precision)
Fmul = 490
fmul: Floating Multiply (Double-Precision)
Fnabs = 491
fnabs: Floating Negative Absolute Value
Fneg = 492
fneg: Floating Negate
Fnmadd = 493
fnmadd: Floating Negative Multiply-Add (Double-Precision)
Fnmsub = 494
fnmsub: Floating Negative Multiply-Subtract (Double-Precision)
Frsp = 495
frsp: Floating Round to Single
Frsqrte = 496
frsqrte: Floating Reciprocal Square Root Estimate
Fsel = 497
fsel: Floating Select
Fsub = 498
fsub: Floating Subtract (Double-Precision)
Mcrfs = 499
mcrfs: Move to Condition Register from FPSCR
Mffs = 500
mffs: Move from FPSCR
Mtfsb0 = 501
mtfsb0: Move to FPSCR Bit 0
Mtfsb1 = 502
mtfsb1: Move to FPSCR Bit 1
Mtfsf = 503
mtfsf: Move to FPSCR Fields
Mtfsfi = 504
mtfsfi: Move to FPSCR Field Immediate
Fcfid = 505
fcfid: Floating Convert from Integer Double Word
Fctid = 506
fctid: Floating Convert to Integer Double Word
Fctidz = 507
fctidz: Floating Convert to Integer Double Word with Round toward Zero