Trait Wire 

pub trait Wire: Sized + 'static {
    const PORT: PortType;
    const JIT: Option<JitType>;
    const RESOLVER: Option<DefaultResolver> = None;
    const WIRE_COST: WireCost = crate::ast::WireCost::Data;

    // Required methods
    fn extract(v: &Value) -> Self;
    fn inject(self) -> Value;
}

Rust-type ↔ Value bridge.

Every owned Rust type the macro accepts in a wire position implements this trait. PORT is the static PortType the DSL type-checker uses to route a wire to this slot; JIT tags the type as ridable on the Phase-2 u64 buffer (or None if it stays on the Phase-1 typed-eval path).

Borrow shapes (&str, &[u8], &[T], &serde_json::Value) and polymorphic Value-typed wires are NOT covered here — the macro recognises them syntactically and emits direct match-on-Value extraction at the eval call site. This keeps the trait surface free of lifetime parameters.

extract panics on type mismatch — the DSL type-checker is responsible for routing well-typed Values to each slot before eval runs. A panic here is a “type-checker was lied to” bug, not a normal path.

Required Associated Constants

const PORT: PortType

Static port type for the DSL type-checker.

const JIT: Option<JitType>

JIT carrier classification. Some(_) means the type rides the Phase-2 u64 buffer; None means typed-eval only.

Provided Associated Constants

const RESOLVER: Option<DefaultResolver> = None

SRD-53 §“Source-string call-site sugar” — auto-resolver for Str-typed upstream wires feeding this slot. None (the default) disables auto-promotion; the workload must supply the wire’s actual port type directly. Set via the Resolved<R, T> marker wrapper.

const WIRE_COST: WireCost = crate::ast::WireCost::Data

SRD-15 §“WireCost::Config” — cost class for this wire. Defaults to WireCost::Data (cheap per-cycle input). Set to WireCost::Config via the Config<T> marker wrapper to signal that the wire is rarely-changing and the compiler should warn on cycle-time binding.

Required Methods

fn extract(v: &Value) -> Self

Pull a typed value out of a Value wire.

fn inject(self) -> Value

Push a typed value back into the Value outputs stream.

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementations on Foreign Types

impl Wire for Arc<Value>

const PORT: PortType = PortType::Json

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Arc<[u8]>

const PORT: PortType = PortType::Bytes

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Arc<dyn Any + Send + Sync>

Arc<dyn Any + Send + Sync> — opaque Handle wire. The body receives the runtime-typed handle directly; downcast is the operator’s responsibility. Use Resolved<R, T> when the node wants a typed Handle with SRD-53 source-string auto-promotion sugar; use this raw shape when the body needs to handle multiple inner types via runtime dispatch.

const PORT: PortType = PortType::Handle

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Arc<str>

Arc<str> — zero-copy shared string handle. Reading extracts the existing Arc<str> from Value::Str (refcount bump only); injecting wraps directly. Nodes whose hot path emits the same string per cycle (lookup table outputs, fixed-value selectors) should use this instead of String to avoid the per-cycle to_string() allocation.

const PORT: PortType = PortType::Str

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Box<dyn ReflectedValue>

Box<dyn ReflectedValue> — Ext (adapter-typed) wire with dynamic downcast left to the body. Use Ext<T> when the inner type is known at codegen; use this when a node needs to dispatch on the runtime ReflectedValue::type_name.

const PORT: PortType = PortType::Ext

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for String

const PORT: PortType = PortType::Str

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<f16>

const PORT: PortType = PortType::VecF16

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<f32>

const PORT: PortType = PortType::VecF32

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<f64>

const PORT: PortType = PortType::VecF64

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<i8>

const PORT: PortType = PortType::VecI8

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<i16>

const PORT: PortType = PortType::VecI16

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<i32>

const PORT: PortType = PortType::VecI32

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<i64>

const PORT: PortType = PortType::VecI64

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for Vec<u8>

const PORT: PortType = PortType::Bytes

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [f16; 8]

const PORT: PortType = PortType::RegF16x8

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [f32; 4]

const PORT: PortType = PortType::RegF32x4

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [f64; 2]

const PORT: PortType = PortType::RegF64x2

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [i8; 16]

const PORT: PortType = PortType::RegI8x16

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [i16; 8]

const PORT: PortType = PortType::RegI16x8

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [i32; 4]

const PORT: PortType = PortType::RegI32x4

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for [i64; 2]

const PORT: PortType = PortType::RegI64x2

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for bool

const PORT: PortType = PortType::Bool

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for f16

const PORT: PortType = PortType::F16

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for f32

const PORT: PortType = PortType::F32

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for f64

const PORT: PortType = PortType::F64

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for i8

const PORT: PortType = PortType::I8

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for i16

const PORT: PortType = PortType::I16

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for i32

const PORT: PortType = PortType::I32

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for i64

const PORT: PortType = PortType::I64

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for i128

const PORT: PortType = PortType::I128

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for u8

const PORT: PortType = PortType::U8

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for u16

const PORT: PortType = PortType::U16

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for u32

const PORT: PortType = PortType::U32

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for u64

const PORT: PortType = PortType::U64

const JIT: Option<JitType>

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl Wire for u128

const PORT: PortType = PortType::U128

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

impl<T: Wire> Wire for Option<T>

None-aware wire combinator. Macro auto-emits accepts_none_inputs() -> true when any arg is Option<_>.

const PORT: PortType = T::PORT

const JIT: Option<JitType> = None

fn extract(v: &Value) -> Self

fn inject(self) -> Value

Implementors

impl Wire for Bits128

const PORT: PortType = PortType::Reg128

const JIT: Option<JitType> = None

impl Wire for SliceArc<f16>

const PORT: PortType = PortType::VecF16

const JIT: Option<JitType> = None

impl Wire for SliceArc<f32>

const PORT: PortType = PortType::VecF32

const JIT: Option<JitType> = None

impl Wire for SliceArc<f64>

const PORT: PortType = PortType::VecF64

const JIT: Option<JitType> = None

impl Wire for SliceArc<i8>

const PORT: PortType = PortType::VecI8

const JIT: Option<JitType> = None

impl Wire for SliceArc<i16>

const PORT: PortType = PortType::VecI16

const JIT: Option<JitType> = None

impl Wire for SliceArc<i32>

const PORT: PortType = PortType::VecI32

const JIT: Option<JitType> = None

impl Wire for SliceArc<i64>

const PORT: PortType = PortType::VecI64

const JIT: Option<JitType> = None

impl<R: ResolverKind, T: 'static + Send + Sync> Wire for Resolved<R, T>

const PORT: PortType = PortType::Handle

const JIT: Option<JitType> = None

const RESOLVER: Option<DefaultResolver>

impl<T: ReflectedValue + Clone + 'static> Wire for Ext<T>

const PORT: PortType = PortType::Ext

const JIT: Option<JitType> = None

impl<T: Wire> Wire for Config<T>

const PORT: PortType = T::PORT

const JIT: Option<JitType> = T::JIT

const RESOLVER: Option<DefaultResolver> = T::RESOLVER

const WIRE_COST: WireCost = crate::ast::WireCost::Config